/[gxemul]/trunk/src/include/adb_viareg.h
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Contents of /trunk/src/include/adb_viareg.h

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 7608 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /* GXemul: $Id: adb_viareg.h,v 1.1 2005/11/29 05:25:29 debug Exp $ */
2 /* $NetBSD: viareg.h,v 1.4 2001/06/19 12:02:56 simonb Exp $ */
3
4 #ifndef ADB_VIAREG_H
5 #define ADB_VIAREG_H
6
7 /*-
8 * Copyright (C) 1993 Allen K. Briggs, Chris P. Caputo,
9 * Michael L. Finch, Bradley A. Grantham, and
10 * Lawrence A. Kesteloot
11 * All rights reserved.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 * must display the following acknowledgement:
23 * This product includes software developed by the Alice Group.
24 * 4. The names of the Alice Group or any of its members may not be used
25 * to endorse or promote products derived from this software without
26 * specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE ALICE GROUP ``AS IS'' AND ANY EXPRESS OR
29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
31 * IN NO EVENT SHALL THE ALICE GROUP BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
40 /*
41
42 Prototype VIA control definitions
43
44 06/04/92,22:33:57 BG Let's see what I can do.
45
46 */
47
48
49 /* VIA1 data register A */
50 #define DA1I_vSCCWrReq 0x80
51 #define DA1O_vPage2 0x40
52 #define DA1I_CPU_ID1 0x40
53 #define DA1O_vHeadSel 0x20
54 #define DA1O_vOverlay 0x10
55 #define DA1O_vSync 0x08
56 #define DA1O_RESERVED2 0x04
57 #define DA1O_RESERVED1 0x02
58 #define DA1O_RESERVED0 0x01
59
60 /* VIA1 data register B */
61 #define DB1I_Par_Err 0x80
62 #define DB1O_vSndEnb 0x80
63 #define DB1O_Par_Enb 0x40
64 #define DB1O_vFDesk2 0x20
65 #define DB1O_vFDesk1 0x10
66 #define DB1I_vFDBInt 0x08
67 #define DB1O_rTCEnb 0x04
68 #define DB1O_rTCCLK 0x02
69 #define DB1O_rTCData 0x01
70 #define DB1I_rTCData 0x01
71
72 /* VIA2 data register A */
73 #define DA2O_v2Ram1 0x80
74 #define DA2O_v2Ram0 0x40
75 #define DA2I_v2IRQ0 0x40
76 #define DA2I_v2IRQE 0x20
77 #define DA2I_v2IRQD 0x10
78 #define DA2I_v2IRQC 0x08
79 #define DA2I_v2IRQB 0x04
80 #define DA2I_v2IRQA 0x02
81 #define DA2I_v2IRQ9 0x01
82
83 /* VIA2 data register B */
84 #define DB2O_v2VBL 0x80
85 #define DB2O_Par_Test 0x80
86 #define DB2I_v2SNDEXT 0x40
87 #define DB2I_v2TM0A 0x20
88 #define DB2I_v2TM1A 0x10
89 #define DB2I_vFC3 0x08
90 #define DB2O_vFC3 0x08
91 #define DB2O_v2PowerOff 0x04
92 #define DB2O_v2BusLk 0x02
93 #define DB2O_vCDis 0x01
94 #define DB2O_CEnable 0x01
95
96 /*
97 * VIA1 interrupts
98 */
99 #define VIA1_T1 6
100 #define VIA1_T2 5
101 #define VIA1_ADBCLK 4
102 #define VIA1_ADBDATA 3
103 #define VIA1_ADBRDY 2
104 #define VIA1_VBLNK 1
105 #define VIA1_ONESEC 0
106
107 /* VIA1 interrupt bits */
108 #define V1IF_IRQ 0x80
109 #define V1IF_T1 (1 << VIA1_T1)
110 #define V1IF_T2 (1 << VIA1_T2)
111 #define V1IF_ADBCLK (1 << VIA1_ADBCLK)
112 #define V1IF_ADBDATA (1 << VIA1_ADBDATA)
113 #define V1IF_ADBRDY (1 << VIA1_ADBRDY)
114 #define V1IF_VBLNK (1 << VIA1_VBLNK)
115 #define V1IF_ONESEC (1 << VIA1_ONESEC)
116
117 /*
118 * VIA2 interrupts
119 */
120 #define VIA2_T1 6
121 #define VIA2_T2 5
122 #define VIA2_ASC 4
123 #define VIA2_SCSIIRQ 3
124 #define VIA2_EXPIRQ 2
125 #define VIA2_SLOTINT 1
126 #define VIA2_SCSIDRQ 0
127
128 /* VIA2 interrupt bits */
129 #define V2IF_IRQ 0x80
130 #define V2IF_T1 (1 << VIA2_T1)
131 #define V2IF_T2 (1 << VIA2_T2)
132 #define V2IF_ASC (1 << VIA2_ASC)
133 #define V2IF_SCSIIRQ (1 << VIA2_SCSIIRQ)
134 #define V2IF_EXPIRQ (1 << VIA2_EXPIRQ)
135 #define V2IF_SLOTINT (1 << VIA2_SLOTINT)
136 #define V2IF_SCSIDRQ (1 << VIA2_SCSIDRQ)
137
138 #define VIA1_INTS (V1IF_T1 | V1IF_ADBRDY)
139 #define VIA2_INTS (V2IF_T1 | V2IF_ASC | V2IF_SCSIIRQ | V2IF_SLOTINT | \
140 V2IF_SCSIDRQ)
141
142 #define RBV_INTS (V2IF_T1 | V2IF_ASC | V2IF_SCSIIRQ | V2IF_SLOTINT | \
143 V2IF_SCSIDRQ | V1IF_ADBRDY)
144
145 #define ACR_T1LATCH 0x40
146
147 #if 0
148 extern volatile unsigned char *Via1Base;
149 #endif
150 #define VIA1_addr Via1Base /* at PA 0x50f00000 */
151 #define VIA2OFF 1 /* VIA2 addr = VIA1_addr * 0x2000 */
152 #define RBVOFF 0x13 /* RBV addr = VIA1_addr * 0x13000 */
153
154 #define VIA1 0
155 #define VIA2 0
156
157 /* VIA interface registers */
158 #define vBufB 0x0000 /* register B */
159 #define vBufA 0x0200 /* register A */
160 #define vDirB 0x0400 /* data direction register */
161 #define vDirA 0x0600 /* data direction register */
162 #define vT1C 0x0800
163 #define vT1CH 0x0a00
164 #define vT1L 0x0c00
165 #define vT1LH 0x0e00
166 #define vT2C 0x1000
167 #define vT2CH 0x1200
168 #define vSR 0x1400 /* shift register */
169 #define vACR 0x1600 /* aux control register */
170 #define vPCR 0x1800 /* peripheral control register */
171 #define vIFR 0x1a00 /* interrupt flag register */
172 #define vIER 0x1c00 /* interrupt enable register */
173
174 /* RBV interface registers */
175 #define rBufB 0 /* register B */
176 #define rBufA 2 /* register A */
177 #define rIFR 0x3 /* interrupt flag register (writes?) */
178 #define rIER 0x13 /* interrupt enable register */
179 #define rMonitor 0x10 /* Monitor type */
180 #define rSlotInt 0x12 /* Slot interrupt */
181
182 /* RBV monitor type flags and masks */
183 #define RBVDepthMask 0x07 /* depth in bits */
184 #define RBVMonitorMask 0x38 /* Type numbers */
185 #define RBVOff 0x40 /* monitor turn off */
186 #define RBVMonIDNone 0x38 /* What RBV actually has for no video */
187 #define RBVMonIDOff 0x0 /* What rbv_vidstatus() returns for no video */
188 #define RBVMonID15BWP 0x08 /* BW portrait */
189 #define RBVMonIDRGB 0x10 /* color monitor */
190 #define RBVMonIDRGB15 0x28 /* 15 inch RGB */
191 #define RBVMonIDBW 0x30 /* No internal video */
192
193 #define via_reg(v, r) (*(Via1Base + (r)))
194
195 #if 0
196 #include <machine/pio.h>
197
198 static __inline void via_reg_and(int, int, int);
199 static __inline void via_reg_or(int, int, int);
200 static __inline void via_reg_xor(int, int, int);
201 static __inline void write_via_reg(int, int, int);
202 static __inline int read_via_reg(int, int);
203
204 static __inline void
205 via_reg_and(ign, reg, val)
206 int ign, reg, val;
207 {
208 volatile unsigned char *addr = Via1Base + reg;
209
210 out8(addr, in8(addr) & val);
211 }
212
213 static __inline void
214 via_reg_or(ign, reg, val)
215 int ign, reg, val;
216 {
217 volatile unsigned char *addr = Via1Base + reg;
218
219 out8(addr, in8(addr) | val);
220 }
221
222 static __inline void
223 via_reg_xor(ign, reg, val)
224 int ign, reg, val;
225 {
226 volatile unsigned char *addr = Via1Base + reg;
227
228 out8(addr, in8(addr) ^ val);
229 }
230
231 static __inline int
232 read_via_reg(ign, reg)
233 int ign, reg;
234 {
235 volatile unsigned char *addr = Via1Base + reg;
236
237 return in8(addr);
238 }
239
240 static __inline void
241 write_via_reg(ign, reg, val)
242 int ign, reg, val;
243 {
244 volatile unsigned char *addr = Via1Base + reg;
245
246 out8(addr, val);
247 }
248
249
250
251 #define vDirA_ADBState 0x30
252
253 void via_init __P((void));
254 int rbv_vidstatus __P((void));
255 void via_shutdown __P((void));
256 void via_set_modem __P((int));
257 int add_nubus_intr __P((int, void (*) __P((void *, int)), void *));
258 void enable_nubus_intr __P((void));
259 void via1_register_irq __P((int, void (*)(void *), void *));
260 void via2_register_irq __P((int, void (*)(void *), void *));
261
262 extern void (*via1itab[7]) __P((void *));
263 extern void (*via2itab[7]) __P((void *));
264 #endif
265
266 #endif /* ADB_VIAREG_H */

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