/[gxemul]/trunk/src/devices/pci_vt82c586.c
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Contents of /trunk/src/devices/pci_vt82c586.c

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Revision 4 - (show annotations)
Mon Oct 8 16:18:00 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 3774 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============


1 /*
2 * Copyright (C) 2004 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: pci_vt82c586.c,v 1.12 2005/02/26 18:00:38 debug Exp $
29 *
30 * VIATECH VT82C586 devices:
31 *
32 * vt82c586_isa PCI->ISA bridge
33 * vt82c586_ide IDE controller
34 *
35 * TODO: This more or less just a dummy device, so far.
36 */
37
38 #include <stdio.h>
39 #include <stdlib.h>
40 #include <string.h>
41
42 #include "memory.h"
43 #include "misc.h"
44 #include "devices.h"
45 #include "bus_pci.h"
46
47
48 #define PCI_VENDOR_VIATECH 0x1106 /* VIA Technologies */
49 #define PCI_PRODUCT_VIATECH_VT82C586_IDE 0x1571 /* VT82C586 (Apollo VP)
50 IDE Controller */
51 #define PCI_PRODUCT_VIATECH_VT82C586_ISA 0x0586 /* VT82C586 (Apollo VP)
52 PCI-ISA Bridge */
53
54
55 /*
56 * pci_vt82c586_isa_rr():
57 */
58 uint32_t pci_vt82c586_isa_rr(int reg)
59 {
60 /* NetBSD reads from 0x04, 0x08, 0x3c, 0x0c, 0x2c during init */
61
62 switch (reg) {
63 case 0x00:
64 return PCI_VENDOR_VIATECH +
65 (PCI_PRODUCT_VIATECH_VT82C586_ISA << 16);
66 case 0x04:
67 return 0xffffffff; /* ??? */
68 case 0x08:
69 /* Revision 37 or 39 */
70 return PCI_CLASS_CODE(PCI_CLASS_BRIDGE,
71 PCI_SUBCLASS_BRIDGE_ISA, 0) + 39;
72 case 0x0c:
73 /* Bit 7 of Header-type byte ==> multi-function device */
74 return 0x00800000;
75 default:
76 return 0;
77 }
78 }
79
80
81 /*
82 * pci_vt82c586_isa_init():
83 */
84 void pci_vt82c586_isa_init(struct machine *machine, struct memory *mem)
85 {
86 }
87
88
89 /*
90 * pci_vt82c586_ide_rr():
91 */
92 uint32_t pci_vt82c586_ide_rr(int reg)
93 {
94 /* NetBSD reads from 0x04, 0x08, 0x3c, 0x0c, 0x2c during init */
95
96 switch (reg) {
97 case 0x00:
98 return PCI_VENDOR_VIATECH +
99 (PCI_PRODUCT_VIATECH_VT82C586_IDE << 16);
100 case 0x04:
101 return 0xffffffff; /* ??? */
102 case 0x08:
103 /* Possibly not correct: */
104 return PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE,
105 PCI_SUBCLASS_MASS_STORAGE_IDE, 0) + 0x01;
106 case 0x40: /* APO_IDECONF */
107 /* channel 0 and 1 enabled */
108 return 0x00000003;
109 default:
110 return 0;
111 }
112 }
113
114
115 /*
116 * pci_vt82c586_ide_init():
117 */
118 void pci_vt82c586_ide_init(struct machine *machine, struct memory *mem)
119 {
120 /*
121 * TODO: what about these base addresses and interrupt
122 * numbers? They work for Cobalt... 7 = PCI interrupt?? (TODO)
123 */
124 dev_wdc_init(machine, mem, 0x100001f0, 6, 0); /* primary */
125 dev_wdc_init(machine, mem, 0x10000170, 6, 2); /* secondary */
126 }
127

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