src/devices/pci_dec21143.c

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: pci_dec21143.c,v 1.10 2005/10/25 06:49:08 debug Exp $
 *
 *  DEC 21143 ("Tulip") PCI ethernet.
 *
 *  TODO:  This is just a dummy device, so far.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "devices.h"
#include "memory.h"
#include "misc.h"

#include "bus_pci.h"
#include "tulipreg.h"


#define debug fatal

#define PCI_VENDOR_DEC          0x1011 /* Digital Equipment */
#define PCI_PRODUCT_DEC_21142   0x0019 /* DECchip 21142/21143 10/100 Ethernet */


struct dec21143_data {
        int     dummy;
};


/*
 *  dev_dec21143_access():
 *
 *  Memory access.
 */
int dev_dec21143_access(struct cpu *cpu, struct memory *mem,
        uint64_t relative_addr, unsigned char *data, size_t len,
        int writeflag, void *extra)
{
        struct dec21143_data *d = extra;
        uint64_t idata = 0, odata = 0;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        switch (relative_addr) {

        default:if (writeflag == MEM_READ)
                        debug("[ dec_21143: read from 0x%02x ]\n",
                            (int)relative_addr);
                else
                        debug("[ dec_21143: write to  0x%02x: 0x%02x ]\n",
                            (int)relative_addr, (int)idata);
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


/*
 *  dev_dec21143_io_access():
 *
 *  I/O port access.
 */
int dev_dec21143_io_access(struct cpu *cpu, struct memory *mem,
        uint64_t relative_addr, unsigned char *data, size_t len,
        int writeflag, void *extra)
{
        struct dec21143_data *d = extra;
        uint64_t idata = 0, odata = 0;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        switch (relative_addr) {
        default:if (writeflag == MEM_READ)
                        debug("[ dec_21143_io: read from 0x%02x ]\n",
                            (int)relative_addr);
                else
                        debug("[ dec_21143_io: write to  0x%02x: 0x%02x ]\n",
                            (int)relative_addr, (int)idata);
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


/*
 *  pci_dec21143_rr():
 */
uint32_t pci_dec21143_rr(int reg)
{
        switch (reg) {
        case 0x00:
                return PCI_VENDOR_DEC + (PCI_PRODUCT_DEC_21142 << 16);
        case 0x04:
                return 0xffffffff;
        case 0x08:
                /*  Revision 4.1  */
                return PCI_CLASS_CODE(PCI_CLASS_NETWORK,
                    PCI_SUBCLASS_NETWORK_ETHERNET, 0) + 0x41;
        case 0x10:
                /*  1ca00000, I/O space  (I have no idea about these...)  */
                return 0x00200001;  /*  CATS  */
                return 0x9ca00001;  /*  cobalt  */
        case 0x14:
                /*  1ca10000, mem space  (I have no idea about these...)  */
                return 0x00210000;      /*  CATS  */
                return 0x9ca10000;      /*  cobalt  */
        case 0x3c:
                return 0x00000800;
/*      cobalt  return 0x00000100;        interrupt pin A  */
        default:
                return 0;
        }
}


/*
 *  pci_dec21143_init():
 */
void pci_dec21143_init(struct machine *machine, struct memory *mem)
{
        struct dec21143_data *d;
        d = malloc(sizeof(struct dec21143_data));
        if (d == NULL) {
                fprintf(stderr, "out of memory\n");
                exit(1);
        }
        memset(d, 0, sizeof(struct dec21143_data));

        /*  TODO: This only works for CATS.  */
        memory_device_register(mem, "dec21143", 0x80200000,
            0x10000, dev_dec21143_io_access, d, MEM_DEFAULT, NULL);
        memory_device_register(mem, "dec21143", 0x80210000,
            0x10000, dev_dec21143_access, d, MEM_DEFAULT, NULL);
}

1	dpavlin	4	/*
2	dpavlin	18	* Copyright (C) 2005 Anders Gavare. All rights reserved.
3	dpavlin	4	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	18	* $Id: pci_dec21143.c,v 1.10 2005/10/25 06:49:08 debug Exp $
29	dpavlin	4	*
30	dpavlin	18	* DEC 21143 ("Tulip") PCI ethernet.
31	dpavlin	4	*
32			* TODO: This is just a dummy device, so far.
33			*/
34
35			#include <stdio.h>
36			#include <stdlib.h>
37			#include <string.h>
38
39			#include "devices.h"
40			#include "memory.h"
41			#include "misc.h"
42
43			#include "bus_pci.h"
44	dpavlin	18	#include "tulipreg.h"
45	dpavlin	4
46
47	dpavlin	18	#define debug fatal
48
49	dpavlin	4	#define PCI_VENDOR_DEC 0x1011 /* Digital Equipment */
50			#define PCI_PRODUCT_DEC_21142 0x0019 /* DECchip 21142/21143 10/100 Ethernet */
51
52
53	dpavlin	18	struct dec21143_data {
54			int dummy;
55			};
56
57
58	dpavlin	4	/*
59	dpavlin	18	* dev_dec21143_access():
60			*
61			* Memory access.
62			*/
63			int dev_dec21143_access(struct cpu cpu, struct memory mem,
64			uint64_t relative_addr, unsigned char *data, size_t len,
65			int writeflag, void *extra)
66			{
67			struct dec21143_data *d = extra;
68			uint64_t idata = 0, odata = 0;
69
70			if (writeflag == MEM_WRITE)
71			idata = memory_readmax64(cpu, data, len);
72
73			switch (relative_addr) {
74
75			default:if (writeflag == MEM_READ)
76			debug("[ dec_21143: read from 0x%02x ]\n",
77			(int)relative_addr);
78			else
79			debug("[ dec_21143: write to 0x%02x: 0x%02x ]\n",
80			(int)relative_addr, (int)idata);
81			}
82
83			if (writeflag == MEM_READ)
84			memory_writemax64(cpu, data, len, odata);
85
86			return 1;
87			}
88
89
90			/*
91			* dev_dec21143_io_access():
92			*
93			* I/O port access.
94			*/
95			int dev_dec21143_io_access(struct cpu cpu, struct memory mem,
96			uint64_t relative_addr, unsigned char *data, size_t len,
97			int writeflag, void *extra)
98			{
99			struct dec21143_data *d = extra;
100			uint64_t idata = 0, odata = 0;
101
102			if (writeflag == MEM_WRITE)
103			idata = memory_readmax64(cpu, data, len);
104
105			switch (relative_addr) {
106			default:if (writeflag == MEM_READ)
107			debug("[ dec_21143_io: read from 0x%02x ]\n",
108			(int)relative_addr);
109			else
110			debug("[ dec_21143_io: write to 0x%02x: 0x%02x ]\n",
111			(int)relative_addr, (int)idata);
112			}
113
114			if (writeflag == MEM_READ)
115			memory_writemax64(cpu, data, len, odata);
116
117			return 1;
118			}
119
120
121			/*
122	dpavlin	4	* pci_dec21143_rr():
123			*/
124			uint32_t pci_dec21143_rr(int reg)
125			{
126			switch (reg) {
127			case 0x00:
128			return PCI_VENDOR_DEC + (PCI_PRODUCT_DEC_21142 << 16);
129			case 0x04:
130			return 0xffffffff;
131			case 0x08:
132			/* Revision 4.1 */
133	dpavlin	14	return PCI_CLASS_CODE(PCI_CLASS_NETWORK,
134			PCI_SUBCLASS_NETWORK_ETHERNET, 0) + 0x41;
135	dpavlin	4	case 0x10:
136			/* 1ca00000, I/O space (I have no idea about these...) */
137	dpavlin	18	return 0x00200001; /* CATS */
138			return 0x9ca00001; /* cobalt */
139	dpavlin	4	case 0x14:
140			/* 1ca10000, mem space (I have no idea about these...) */
141	dpavlin	18	return 0x00210000; /* CATS */
142			return 0x9ca10000; /* cobalt */
143	dpavlin	4	case 0x3c:
144	dpavlin	18	return 0x00000800;
145			/* cobalt return 0x00000100; interrupt pin A */
146	dpavlin	4	default:
147			return 0;
148			}
149			}
150
151
152			/*
153			* pci_dec21143_init():
154			*/
155			void pci_dec21143_init(struct machine machine, struct memory mem)
156			{
157	dpavlin	18	struct dec21143_data *d;
158			d = malloc(sizeof(struct dec21143_data));
159			if (d == NULL) {
160			fprintf(stderr, "out of memory\n");
161			exit(1);
162			}
163			memset(d, 0, sizeof(struct dec21143_data));
164
165			/* TODO: This only works for CATS. */
166			memory_device_register(mem, "dec21143", 0x80200000,
167			0x10000, dev_dec21143_io_access, d, MEM_DEFAULT, NULL);
168			memory_device_register(mem, "dec21143", 0x80210000,
169			0x10000, dev_dec21143_access, d, MEM_DEFAULT, NULL);
170	dpavlin	4	}
171