/[gxemul]/trunk/src/devices/dev_z8530.c
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Annotation of /trunk/src/devices/dev_z8530.c

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Revision 22 - (hide annotations)
Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 dpavlin 22 /*
2     * Copyright (C) 2004-2006 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28     * $Id: dev_z8530.c,v 1.5 2006/02/09 20:02:59 debug Exp $
29     *
30     * Zilog "zs" serial controller (Z8530).
31     *
32     * Features:
33     * o) Two channels, 0 = "channel B", 1 = "channel A".
34     *
35     * This is a work in progress... TODOs include:
36     * o) Implement more of the register set.
37     * o) Verify that it works with other guest OSes than NetBSD and OpenBSD.
38     * o) Implement DMA!
39     */
40    
41     #include <stdio.h>
42     #include <stdlib.h>
43     #include <string.h>
44    
45     #include "console.h"
46     #include "cpu.h"
47     #include "device.h"
48     #include "machine.h"
49     #include "memory.h"
50     #include "misc.h"
51    
52     #include "z8530reg.h"
53    
54    
55     #define debug fatal
56    
57     #define ZS_TICK_SHIFT 14
58     #define ZS_N_REGS 16
59     #define DEV_Z8530_LENGTH 4
60    
61     struct z8530_data {
62     int irq_nr;
63     int dma_irq_nr;
64     int irq_asserted;
65    
66     int in_use;
67     int addr_mult;
68    
69     /* 2 of everything, because there are two channels. */
70     int console_handle[2];
71     int reg_select[2];
72     uint8_t rr[2][ZS_N_REGS];
73     uint8_t wr[2][ZS_N_REGS];
74     };
75    
76    
77     /*
78     * check_incoming():
79     */
80     static void check_incoming(struct cpu *cpu, struct z8530_data *d)
81     {
82     if (console_charavail(d->console_handle[0])) {
83     d->rr[1][3] |= ZSRR3_IP_B_RX;
84     d->rr[0][0] |= ZSRR0_RX_READY;
85     }
86     if (console_charavail(d->console_handle[1])) {
87     d->rr[1][3] |= ZSRR3_IP_A_RX;
88     d->rr[1][0] |= ZSRR0_RX_READY;
89     }
90     }
91    
92    
93     /*
94     * dev_z8530_tick():
95     */
96     void dev_z8530_tick(struct cpu *cpu, void *extra)
97     {
98     struct z8530_data *d = (struct z8530_data *) extra;
99     int asserted = 0;
100    
101     if (d->rr[1][3] & ZSRR3_IP_B_TX && d->wr[0][1] & ZSWR1_TIE)
102     asserted = 1;
103     if (d->rr[1][3] & ZSRR3_IP_A_TX && d->wr[1][1] & ZSWR1_TIE)
104     asserted = 1;
105    
106     d->rr[1][3] &= ~(ZSRR3_IP_B_RX | ZSRR3_IP_A_RX);
107     if (!asserted)
108     check_incoming(cpu, d);
109    
110     if (d->rr[1][3] & ZSRR3_IP_B_RX && (d->wr[0][1]&0x18) != ZSWR1_RIE_NONE)
111     asserted = 1;
112     if (d->rr[1][3] & ZSRR3_IP_A_RX && (d->wr[1][1]&0x18) != ZSWR1_RIE_NONE)
113     asserted = 1;
114    
115     if (!(d->wr[1][9] & ZSWR9_MASTER_IE))
116     asserted = 0;
117    
118     if (asserted)
119     cpu_interrupt(cpu, d->irq_nr);
120    
121     if (d->irq_asserted && !asserted)
122     cpu_interrupt_ack(cpu, d->irq_nr);
123    
124     d->irq_asserted = asserted;
125     }
126    
127    
128     /*
129     * dev_z8530_access():
130     */
131     DEVICE_ACCESS(z8530)
132     {
133     struct z8530_data *d = extra;
134     uint64_t idata = 0, odata = 0;
135     int port_nr;
136    
137     if (writeflag == MEM_WRITE)
138     idata = memory_readmax64(cpu, data, len);
139    
140     /* Both ports are always ready to transmit: */
141     d->rr[0][0] |= ZSRR0_TX_READY | ZSRR0_DCD | ZSRR0_CTS;
142     d->rr[1][0] |= ZSRR0_TX_READY | ZSRR0_DCD | ZSRR0_CTS;
143    
144     relative_addr /= d->addr_mult;
145    
146     port_nr = relative_addr / 2;
147     relative_addr &= 1;
148    
149     if (relative_addr == 0) {
150     /* Register access: */
151     if (writeflag == MEM_READ) {
152     odata = d->rr[port_nr][d->reg_select[port_nr]];
153     if (d->reg_select[port_nr] != 0)
154     debug("[ z8530: read from port %i reg %2i: "
155     "0x%02x ]\n", port_nr, d->reg_select[
156     port_nr], (int)odata);
157     d->reg_select[port_nr] = 0;
158     } else {
159     if (d->reg_select[port_nr] == 0) {
160     d->reg_select[port_nr] = idata & 15;
161     } else {
162     d->wr[port_nr][d->reg_select[port_nr]] = idata;
163     switch (d->reg_select[port_nr]) {
164     case 8: /* Interrupt ack: */
165     if (idata == ZSWR0_CLR_INTR)
166     d->rr[1][3] = 0;
167     break;
168     default:debug("[ z8530: write to port %i reg "
169     "%2i: 0x%02x ]\n", port_nr, d->
170     reg_select[port_nr], (int)idata);
171     }
172     d->reg_select[port_nr] = 0;
173     }
174     }
175     } else {
176     /* Data access: */
177     if (writeflag == MEM_READ) {
178     int x = console_readchar(d->console_handle[port_nr]);
179     d->rr[port_nr][0] &= ~ZSRR0_RX_READY;
180     odata = x < 0? 0 : x;
181     } else {
182     idata &= 255;
183     if (idata != 0)
184     console_putchar(d->console_handle[port_nr],
185     idata);
186     if (1 /* d->wr[port_nr][1] & ZSWR1_TIE */) {
187     if (port_nr == 0)
188     d->rr[1][3] |= ZSRR3_IP_B_TX;
189     else
190     d->rr[1][3] |= ZSRR3_IP_A_TX;
191     }
192     }
193     }
194    
195     if (writeflag == MEM_READ)
196     memory_writemax64(cpu, data, len, odata);
197    
198     dev_z8530_tick(cpu, extra);
199    
200     return 1;
201     }
202    
203    
204     DEVINIT(z8530)
205     {
206     struct z8530_data *d = malloc(sizeof(struct z8530_data));
207     char tmp[100];
208    
209     if (d == NULL) {
210     fprintf(stderr, "out of memory\n");
211     exit(1);
212     }
213     memset(d, 0, sizeof(struct z8530_data));
214     d->irq_nr = devinit->irq_nr;
215     d->dma_irq_nr = devinit->dma_irq_nr;
216     d->in_use = devinit->in_use;
217     d->addr_mult = devinit->addr_mult;
218    
219     snprintf(tmp, sizeof(tmp), "%s [ch-b]", devinit->name);
220     d->console_handle[0] = console_start_slave(devinit->machine, tmp,
221     d->in_use);
222     snprintf(tmp, sizeof(tmp), "%s [ch-a]", devinit->name);
223     d->console_handle[1] = console_start_slave(devinit->machine, tmp, 0);
224    
225     if (devinit->name2 != NULL && devinit->name2[0])
226     snprintf(tmp, sizeof(tmp), "%s [%s]", devinit->name,
227     devinit->name2);
228     else
229     snprintf(tmp, sizeof(tmp), "%s", devinit->name);
230    
231     memory_device_register(devinit->machine->memory, tmp, devinit->addr,
232     DEV_Z8530_LENGTH * d->addr_mult, dev_z8530_access, d, DM_DEFAULT,
233     NULL);
234    
235     machine_add_tickfunction(devinit->machine, dev_z8530_tick, d,
236     ZS_TICK_SHIFT);
237    
238     devinit->return_ptr = (void *)(size_t) d->console_handle[0];
239    
240     return 1;
241     }
242    

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