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dpavlin |
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/* |
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* Copyright (C) 2004-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
18 |
* $Id: dev_wdsc.c,v 1.27 2005/10/26 14:37:05 debug Exp $ |
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dpavlin |
4 |
* |
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* WDSC SCSI (WD33C93) controller. |
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* (For SGI-IP22. See sys/arch/sgimips/hpc/sbic* in NetBSD for details.) |
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* |
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* TODO: This device doesn't do much yet. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "cpu.h" |
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#include "devices.h" |
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#include "diskimage.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "wdsc_sbicreg.h" |
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struct wdsc_data { |
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int irq_nr; |
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int controller_nr; |
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int register_select; |
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unsigned char reg[DEV_WDSC_NREGS]; |
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int irq_pending; |
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int buf_allocatedlen; |
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int buf_curptr; |
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unsigned char *buf; |
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int current_phase; |
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struct scsi_transfer *xfer; |
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}; |
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/* |
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* dev_wdsc_tick(): |
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*/ |
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void dev_wdsc_tick(struct cpu *cpu, void *extra) |
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{ |
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struct wdsc_data *d = extra; |
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if (d->irq_pending) |
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cpu_interrupt(cpu, d->irq_nr); |
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else |
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cpu_interrupt_ack(cpu, d->irq_nr); |
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} |
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/* |
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* dev_wdsc_regwrite(): |
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* |
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* Handle writes to WDSC registers. |
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*/ |
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static void dev_wdsc_regwrite(struct cpu *cpu, struct wdsc_data *d, int idata) |
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{ |
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d->reg[d->register_select] = idata & 0xff; |
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debug("[ wdsc: write to register %i", d->register_select); |
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switch (d->register_select) { |
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case SBIC_myid: |
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debug(" (myid): 0x%02x => ", (int)idata); |
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if (idata & SBIC_ID_FS_16_20) |
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debug("16-20MHz, "); |
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if (idata & SBIC_ID_FS_12_15) |
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debug("12-15MHz, "); |
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if (idata & SBIC_ID_RAF) |
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debug("RAF(?), "); |
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if (idata & SBIC_ID_EHP) |
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debug("Parity, "); |
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if (idata & SBIC_ID_EAF) |
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debug("EnableAdvancedFeatures, "); |
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debug("ID=%i", idata & SBIC_ID_MASK); |
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break; |
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case SBIC_control: |
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debug(" (control): 0x%02x =>", (int)idata); |
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if (idata & SBIC_CTL_DMA) |
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debug(" SingleByteDMA"); |
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if (idata & SBIC_CTL_DBA_DMA) |
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debug(" DirectBufferAccess"); |
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if (idata & SBIC_CTL_BURST_DMA) |
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debug(" BurstDMA"); |
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if (idata & SBIC_CTL_HHP) |
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debug(" HaltOnParity"); |
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if (idata & SBIC_CTL_EDI) |
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debug(" EndDisconIntr"); |
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if (idata & SBIC_CTL_IDI) |
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debug(" IntermediateDisconIntr"); |
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if (idata & SBIC_CTL_HA) |
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debug(" HaltOnATN"); |
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if (idata & SBIC_CTL_HSP) |
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debug(" HaltOnParityError"); |
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if (idata == SBIC_CTL_NO_DMA) |
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debug(" PIO"); |
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/* TODO: When/how are interrupts acknowledged? */ |
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if (idata & SBIC_CTL_EDI) |
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d->irq_pending = 0; |
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break; |
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case SBIC_count_hi: |
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debug(" (count_hi): 0x%02x", (int)idata); |
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break; |
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case SBIC_count_med: |
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debug(" (count_med): 0x%02x", (int)idata); |
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break; |
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case SBIC_count_lo: |
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debug(" (count_lo): 0x%02x", (int)idata); |
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break; |
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case SBIC_selid: |
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debug(" (selid): 0x%02x => ", (int)idata); |
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if (idata & SBIC_SID_SCC) |
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debug("SelectCommandChaining, "); |
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if (idata & SBIC_SID_FROM_SCSI) |
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debug("FromSCSI, "); |
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else |
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debug("ToSCSI, "); |
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debug("id %i", idata & SBIC_SID_IDMASK); |
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break; |
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case SBIC_rselid: |
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debug(" (rselid): 0x%02x => ", (int)idata); |
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if (idata & SBIC_RID_ER) |
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debug("EnableReselection, "); |
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if (idata & SBIC_RID_ES) |
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debug("EnableSelection, "); |
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if (idata & SBIC_RID_DSP) |
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debug("DisableSelectParity, "); |
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if (idata & SBIC_RID_SIV) |
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debug("SourceIDValid, "); |
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debug("id %i", idata & SBIC_RID_MASK); |
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break; |
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case SBIC_cmd: |
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debug(" (cmd): 0x%02x => ", (int)idata); |
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/* SBT = Single Byte Transfer */ |
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if (idata & SBIC_CMD_SBT) |
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debug("SBT, "); |
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/* Handle commands: */ |
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switch (idata & SBIC_CMD_MASK) { |
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case SBIC_CMD_RESET: |
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debug("RESET"); |
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d->irq_pending = 1; |
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d->reg[SBIC_csr] = SBIC_CSR_RESET; |
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break; |
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case SBIC_CMD_ABORT: |
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debug("ABORT"); |
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break; |
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case SBIC_CMD_SEL_ATN: |
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debug("SEL_ATN"); |
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d->irq_pending = 1; |
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d->reg[SBIC_csr] = SBIC_CSR_SEL_TIMEO; |
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if (d->controller_nr == 0 && diskimage_exist( |
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cpu->machine, d->reg[SBIC_selid] & |
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dpavlin |
6 |
SBIC_SID_IDMASK, DISKIMAGE_SCSI)) { |
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dpavlin |
4 |
if (d->xfer != NULL) |
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scsi_transfer_free(d->xfer); |
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d->xfer = scsi_transfer_alloc(); |
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/* According to NetBSD, we can go either to |
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SBIC_CSR_MIS_2 | CMD_PHASE, or |
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SBIC_CSR_MIS_2 | MESG_OUT_PHASE. */ |
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d->reg[SBIC_csr] = SBIC_CSR_MIS_2 | CMD_PHASE; |
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d->current_phase = CMD_PHASE; |
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} |
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break; |
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case SBIC_CMD_XFER_INFO: |
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debug("XFER_INFO"); |
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if (d->buf != NULL) |
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free(d->buf); |
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d->buf_allocatedlen = (d->reg[SBIC_count_hi] << 16) |
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+ (d->reg[SBIC_count_med] << 8) + |
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d->reg[SBIC_count_lo]; |
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d->buf = malloc(d->buf_allocatedlen); |
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if (d->buf == NULL) { |
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fprintf(stderr, "out of memory in wdsc\n"); |
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exit(1); |
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} |
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d->buf_curptr = 0; |
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d->irq_pending = 0; |
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break; |
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default: |
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debug("unimplemented command"); |
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} |
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break; |
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case SBIC_data: |
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debug(" (data): 0x%02x", (int)idata); |
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switch (d->reg[SBIC_cmd] & ~SBIC_CMD_SBT) { |
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case SBIC_CMD_XFER_INFO: |
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if (d->buf == NULL || d->buf_curptr >= |
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d->buf_allocatedlen) { |
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fprintf(stderr, "fatal error in wdsc\n"); |
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exit(1); |
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} |
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d->buf[d->buf_curptr++] = idata; |
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if (d->buf_curptr >= d->buf_allocatedlen) { |
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int res; |
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/* |
| 257 |
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* Transfer buf to/from the SCSI unit: |
| 258 |
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*/ |
| 259 |
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| 260 |
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switch (d->current_phase) { |
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case CMD_PHASE: |
| 262 |
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scsi_transfer_allocbuf( |
| 263 |
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&d->xfer->cmd_len, &d->xfer->cmd, |
| 264 |
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d->buf_allocatedlen, 1); |
| 265 |
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memcpy(d->xfer->cmd, d->buf, |
| 266 |
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d->buf_allocatedlen); |
| 267 |
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break; |
| 268 |
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default: |
| 269 |
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fatal("wdsc: unimplemented phase %i!\n", |
| 270 |
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d->current_phase); |
| 271 |
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} |
| 272 |
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| 273 |
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res = diskimage_scsicommand(cpu, |
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d->reg[SBIC_selid] & SBIC_SID_IDMASK, |
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dpavlin |
6 |
DISKIMAGE_SCSI, d->xfer); |
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dpavlin |
4 |
debug("{ res = %i }", res); |
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| 278 |
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d->irq_pending = 1; |
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| 280 |
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if (res == 2) |
| 281 |
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d->reg[SBIC_csr] = SBIC_CSR_XFERRED | |
| 282 |
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DATA_OUT_PHASE; |
| 283 |
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else |
| 284 |
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d->reg[SBIC_csr] = SBIC_CSR_XFERRED | |
| 285 |
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DATA_IN_PHASE; |
| 286 |
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| 287 |
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/* status phase? msg in and msg out? */ |
| 288 |
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} |
| 289 |
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break; |
| 290 |
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default: |
| 291 |
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fatal("[ wdsc: don't know how to handle data for " |
| 292 |
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"cmd = 0x%02x ]\n", d->reg[SBIC_cmd]); |
| 293 |
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} |
| 294 |
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| 295 |
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break; |
| 296 |
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| 297 |
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default: |
| 298 |
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debug(" (TODO): 0x%02x", (int)idata); |
| 299 |
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} |
| 300 |
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| 301 |
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debug(" ]\n"); |
| 302 |
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| 303 |
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/* After writing to a register, advance to the next: */ |
| 304 |
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d->register_select ++; |
| 305 |
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} |
| 306 |
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| 307 |
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| 308 |
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/* |
| 309 |
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* dev_wdsc_access(): |
| 310 |
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*/ |
| 311 |
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int dev_wdsc_access(struct cpu *cpu, struct memory *mem, |
| 312 |
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uint64_t relative_addr, unsigned char *data, size_t len, |
| 313 |
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int writeflag, void *extra) |
| 314 |
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{ |
| 315 |
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int i; |
| 316 |
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struct wdsc_data *d = extra; |
| 317 |
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uint64_t idata = 0, odata = 0; |
| 318 |
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| 319 |
dpavlin |
18 |
if (writeflag == MEM_WRITE) |
| 320 |
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idata = memory_readmax64(cpu, data, len); |
| 321 |
dpavlin |
4 |
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| 322 |
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/* |
| 323 |
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* All registers on the WDSC seem to be accessed by writing the |
| 324 |
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* register number to one address (SBIC_ADDR), and then reading/ |
| 325 |
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* writing another address (SBIC_VAL). |
| 326 |
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* |
| 327 |
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* On SGI-IP22, these are at offset 3 and 7, respectively. |
| 328 |
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* |
| 329 |
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* TODO: If this device is to be used by other machine types, then |
| 330 |
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* this needs to be conditionalized. |
| 331 |
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*/ |
| 332 |
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relative_addr = (relative_addr - 3) / 4; |
| 333 |
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| 334 |
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switch (relative_addr) { |
| 335 |
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| 336 |
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case SBIC_ADDR: |
| 337 |
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/* |
| 338 |
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* Reading the combined ADDR/ASR returns the Status |
| 339 |
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* Register, writing selects which register to access |
| 340 |
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* via SBIC_VAL. |
| 341 |
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*/ |
| 342 |
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if (writeflag == MEM_READ) { |
| 343 |
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odata = SBIC_ASR_DBR; |
| 344 |
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if (d->irq_pending) |
| 345 |
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odata |= SBIC_ASR_INT; |
| 346 |
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| 347 |
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debug("[ wdsc: read from Status Register: %02x ]\n", |
| 348 |
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(int)odata); |
| 349 |
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} else { |
| 350 |
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d->register_select = idata & (DEV_WDSC_NREGS - 1); |
| 351 |
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} |
| 352 |
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break; |
| 353 |
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| 354 |
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case SBIC_VAL: |
| 355 |
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if (writeflag == MEM_READ) { |
| 356 |
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odata = d->reg[d->register_select]; |
| 357 |
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| 358 |
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if (d->register_select == SBIC_csr) { |
| 359 |
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/* TODO: when should interrupts actually be |
| 360 |
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ack:ed? */ |
| 361 |
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d->irq_pending = 0; |
| 362 |
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} |
| 363 |
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| 364 |
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debug("[ wdsc: read from register %i: 0x%02x ]\n", |
| 365 |
|
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d->register_select, (int)odata); |
| 366 |
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} else { |
| 367 |
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dev_wdsc_regwrite(cpu, d, idata & 0xff); |
| 368 |
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} |
| 369 |
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break; |
| 370 |
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| 371 |
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default: |
| 372 |
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/* These should never occur: */ |
| 373 |
|
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if (writeflag==MEM_READ) { |
| 374 |
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fatal("[ wdsc: read from 0x%x:", (int)relative_addr); |
| 375 |
|
|
for (i=0; i<len; i++) |
| 376 |
|
|
fatal(" %02x", data[i]); |
| 377 |
|
|
fatal(" (len=%i) ]\n", len); |
| 378 |
|
|
} else { |
| 379 |
|
|
fatal("[ wdsc: write to 0x%x:", (int)relative_addr); |
| 380 |
|
|
for (i=0; i<len; i++) |
| 381 |
|
|
fatal(" %02x", data[i]); |
| 382 |
|
|
fatal(" (len=%i) ]\n", len); |
| 383 |
|
|
} |
| 384 |
|
|
} |
| 385 |
|
|
|
| 386 |
|
|
if (writeflag == MEM_READ) |
| 387 |
|
|
memory_writemax64(cpu, data, len, odata); |
| 388 |
|
|
|
| 389 |
|
|
dev_wdsc_tick(cpu, extra); |
| 390 |
|
|
|
| 391 |
|
|
return 1; |
| 392 |
|
|
} |
| 393 |
|
|
|
| 394 |
|
|
|
| 395 |
|
|
/* |
| 396 |
|
|
* dev_wdsc_init(): |
| 397 |
|
|
*/ |
| 398 |
|
|
void dev_wdsc_init(struct machine *machine, struct memory *mem, |
| 399 |
|
|
uint64_t baseaddr, int controller_nr, int irq_nr) |
| 400 |
|
|
{ |
| 401 |
|
|
struct wdsc_data *d; |
| 402 |
|
|
|
| 403 |
|
|
d = malloc(sizeof(struct wdsc_data)); |
| 404 |
|
|
if (d == NULL) { |
| 405 |
|
|
fprintf(stderr, "out of memory\n"); |
| 406 |
|
|
exit(1); |
| 407 |
|
|
} |
| 408 |
|
|
memset(d, 0, sizeof(struct wdsc_data)); |
| 409 |
|
|
d->irq_nr = irq_nr; |
| 410 |
|
|
d->controller_nr = controller_nr; |
| 411 |
|
|
|
| 412 |
|
|
memory_device_register(mem, "wdsc", baseaddr, DEV_WDSC_LENGTH, |
| 413 |
|
|
dev_wdsc_access, d, MEM_DEFAULT, NULL); |
| 414 |
|
|
|
| 415 |
|
|
machine_add_tickfunction(machine, dev_wdsc_tick, d, 14); |
| 416 |
|
|
} |
| 417 |
|
|
|
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