/[gxemul]/trunk/src/devices/dev_wdc.c
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Annotation of /trunk/src/devices/dev_wdc.c

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Revision 32 - (hide annotations)
Mon Oct 8 16:20:58 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 26534 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 dpavlin 4 /*
2 dpavlin 22 * Copyright (C) 2004-2006 Anders Gavare. All rights reserved.
3 dpavlin 4 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27 dpavlin 14 *
28 dpavlin 32 * $Id: dev_wdc.c,v 1.69 2006/08/30 17:14:25 debug Exp $
29 dpavlin 14 *
30     * Standard "wdc" IDE controller.
31 dpavlin 4 */
32    
33     #include <stdio.h>
34     #include <stdlib.h>
35     #include <string.h>
36    
37     #include "cpu.h"
38 dpavlin 14 #include "device.h"
39 dpavlin 4 #include "diskimage.h"
40     #include "machine.h"
41     #include "memory.h"
42     #include "misc.h"
43    
44     #include "wdcreg.h"
45    
46 dpavlin 14 #define DEV_WDC_LENGTH 8
47 dpavlin 4 #define WDC_TICK_SHIFT 14
48 dpavlin 18 #define WDC_MAX_SECTORS 512
49     #define WDC_INBUF_SIZE (512*(WDC_MAX_SECTORS+1))
50 dpavlin 4
51 dpavlin 14 /*
52 dpavlin 18 * INT_DELAY: This is an old hack which only exists because (some versions of)
53     * NetBSD for hpcmips have interrupt problems. These problems are probably not
54     * specific to GXemul, but are also triggered on real hardware.
55 dpavlin 14 *
56 dpavlin 18 * See the following URL for more info:
57     * http://mail-index.netbsd.org/port-hpcmips/2004/12/30/0003.html
58 dpavlin 20 *
59     * NetBSD/malta also bugs out if wdc interrupts come too quickly. Hm.
60 dpavlin 14 */
61 dpavlin 4 #define INT_DELAY 1
62    
63 dpavlin 6 extern int quiet_mode;
64    
65 dpavlin 4 /* #define debug fatal */
66    
67     struct wdc_data {
68     int irq_nr;
69 dpavlin 22 int addr_mult;
70 dpavlin 4 int base_drive;
71 dpavlin 14 int data_debug;
72 dpavlin 30 int io_enabled;
73 dpavlin 4
74 dpavlin 14 /* Cached values: */
75     int cyls[2];
76     int heads[2];
77     int sectors_per_track[2];
78 dpavlin 4
79 dpavlin 20 unsigned char *inbuf;
80 dpavlin 4 int inbuf_head;
81     int inbuf_tail;
82    
83 dpavlin 14 int delayed_interrupt;
84 dpavlin 20 int int_asserted;
85    
86 dpavlin 4 int write_in_progress;
87     int write_count;
88     int64_t write_offset;
89    
90     int error;
91     int precomp;
92     int seccnt;
93     int sector;
94     int cyl_lo;
95     int cyl_hi;
96     int sectorsize;
97     int lba;
98     int drive;
99     int head;
100     int cur_command;
101 dpavlin 20
102     int atapi_cmd_in_progress;
103     int atapi_phase;
104     struct scsi_transfer *atapi_st;
105     int atapi_len;
106 dpavlin 22 size_t atapi_received;
107 dpavlin 20
108     unsigned char identify_struct[512];
109 dpavlin 4 };
110    
111    
112 dpavlin 20 #define COMMAND_RESET 0x100
113    
114    
115 dpavlin 4 /*
116     * dev_wdc_tick():
117     */
118     void dev_wdc_tick(struct cpu *cpu, void *extra)
119     {
120     struct wdc_data *d = extra;
121 dpavlin 20 int old_di = d->delayed_interrupt;
122 dpavlin 4
123 dpavlin 20 if (d->delayed_interrupt)
124 dpavlin 4 d->delayed_interrupt --;
125    
126 dpavlin 20 if (old_di == 1 || d->int_asserted) {
127     cpu_interrupt(cpu, d->irq_nr);
128     d->int_asserted = 1;
129 dpavlin 4 }
130     }
131    
132    
133     /*
134 dpavlin 30 * wdc_set_io_enabled():
135     *
136     * Set io_enabled to zero to disable the I/O registers temporarily (e.g.
137     * used by PCI code in NetBSD to detect whether multiple controllers collide
138     * in I/O space).
139     *
140     * Return value is old contents of the io_enabled variable.
141     */
142     int wdc_set_io_enabled(struct wdc_data *d, int io_enabled)
143     {
144     int old = d->io_enabled;
145     d->io_enabled = io_enabled;
146     return old;
147     }
148    
149    
150     /*
151 dpavlin 4 * wdc_addtoinbuf():
152     *
153     * Write to the inbuf at its head, read at its tail.
154     */
155     static void wdc_addtoinbuf(struct wdc_data *d, int c)
156     {
157     d->inbuf[d->inbuf_head] = c;
158    
159     d->inbuf_head = (d->inbuf_head + 1) % WDC_INBUF_SIZE;
160     if (d->inbuf_head == d->inbuf_tail)
161 dpavlin 18 fatal("[ wdc_addtoinbuf(): WARNING! wdc inbuf overrun!"
162     " Increase WDC_MAX_SECTORS. ]\n");
163 dpavlin 4 }
164    
165    
166     /*
167     * wdc_get_inbuf():
168     *
169     * Read from the tail of inbuf.
170     */
171     static uint64_t wdc_get_inbuf(struct wdc_data *d)
172     {
173     int c = d->inbuf[d->inbuf_tail];
174    
175     if (d->inbuf_head == d->inbuf_tail) {
176 dpavlin 6 fatal("[ wdc: WARNING! someone is reading too much from the "
177     "wdc inbuf! ]\n");
178 dpavlin 4 return -1;
179     }
180    
181     d->inbuf_tail = (d->inbuf_tail + 1) % WDC_INBUF_SIZE;
182     return c;
183     }
184    
185    
186     /*
187 dpavlin 20 * wdc_initialize_identify_struct():
188 dpavlin 4 */
189     static void wdc_initialize_identify_struct(struct cpu *cpu, struct wdc_data *d)
190     {
191 dpavlin 6 uint64_t total_size;
192 dpavlin 20 int flags, cdrom = 0;
193 dpavlin 14 char namebuf[40];
194 dpavlin 4
195 dpavlin 6 total_size = diskimage_getsize(cpu->machine, d->drive + d->base_drive,
196     DISKIMAGE_IDE);
197 dpavlin 20 if (diskimage_is_a_cdrom(cpu->machine, d->drive + d->base_drive,
198     DISKIMAGE_IDE))
199     cdrom = 1;
200 dpavlin 4
201     memset(d->identify_struct, 0, sizeof(d->identify_struct));
202    
203     /* Offsets are in 16-bit WORDS! High byte, then low. */
204    
205     /* 0: general flags */
206 dpavlin 20 flags = 1 << 6; /* Fixed */
207     if (cdrom)
208     flags = 0x8580; /* ATAPI, CDROM, removable */
209     d->identify_struct[2 * 0 + 0] = flags >> 8;
210     d->identify_struct[2 * 0 + 1] = flags;
211 dpavlin 4
212     /* 1: nr of cylinders */
213 dpavlin 20 d->identify_struct[2 * 1 + 0] = d->cyls[d->drive] >> 8;
214     d->identify_struct[2 * 1 + 1] = d->cyls[d->drive];
215 dpavlin 4
216     /* 3: nr of heads */
217 dpavlin 14 d->identify_struct[2 * 3 + 0] = d->heads[d->drive] >> 8;
218     d->identify_struct[2 * 3 + 1] = d->heads[d->drive];
219 dpavlin 4
220     /* 6: sectors per track */
221 dpavlin 14 d->identify_struct[2 * 6 + 0] = d->sectors_per_track[d->drive] >> 8;
222     d->identify_struct[2 * 6 + 1] = d->sectors_per_track[d->drive];
223 dpavlin 4
224     /* 10-19: Serial number */
225 dpavlin 20 memcpy(&d->identify_struct[2 * 10], "#0 ", 20);
226 dpavlin 4
227     /* 23-26: Firmware version */
228 dpavlin 20 memcpy(&d->identify_struct[2 * 23], "1.0 ", 8);
229 dpavlin 4
230     /* 27-46: Model number */
231 dpavlin 14 if (diskimage_getname(cpu->machine, d->drive + d->base_drive,
232     DISKIMAGE_IDE, namebuf, sizeof(namebuf))) {
233 dpavlin 22 size_t i;
234 dpavlin 14 for (i=0; i<sizeof(namebuf); i++)
235     if (namebuf[i] == 0) {
236     for (; i<sizeof(namebuf); i++)
237     namebuf[i] = ' ';
238     break;
239     }
240     memcpy(&d->identify_struct[2 * 27], namebuf, 40);
241     } else
242     memcpy(&d->identify_struct[2 * 27],
243     "Fake GXemul IDE disk ", 40);
244 dpavlin 4
245     /* 47: max sectors per multitransfer */
246     d->identify_struct[2 * 47 + 0] = 0x80;
247 dpavlin 20 d->identify_struct[2 * 47 + 1] = 128;
248 dpavlin 4
249 dpavlin 20 /* 49: capabilities: */
250     /* (0x200 = LBA, 0x100 = DMA support.) */
251     d->identify_struct[2 * 49 + 0] = 0;
252     d->identify_struct[2 * 49 + 1] = 0;
253    
254     /* 51: PIO timing mode. */
255     d->identify_struct[2 * 51 + 0] = 0x00; /* ? */
256     d->identify_struct[2 * 51 + 1] = 0x00;
257    
258     /* 53: 0x02 = fields 64-70 valid, 0x01 = fields 54-58 valid */
259     d->identify_struct[2 * 53 + 0] = 0x00;
260     d->identify_struct[2 * 53 + 1] = 0x02;
261    
262 dpavlin 4 /* 57-58: current capacity in sectors */
263     d->identify_struct[2 * 57 + 0] = ((total_size / 512) >> 24) % 255;
264     d->identify_struct[2 * 57 + 1] = ((total_size / 512) >> 16) % 255;
265     d->identify_struct[2 * 58 + 0] = ((total_size / 512) >> 8) % 255;
266     d->identify_struct[2 * 58 + 1] = (total_size / 512) & 255;
267    
268 dpavlin 20 /* 60-61: total nr of addressable sectors */
269 dpavlin 4 d->identify_struct[2 * 60 + 0] = ((total_size / 512) >> 24) % 255;
270     d->identify_struct[2 * 60 + 1] = ((total_size / 512) >> 16) % 255;
271     d->identify_struct[2 * 61 + 0] = ((total_size / 512) >> 8) % 255;
272     d->identify_struct[2 * 61 + 1] = (total_size / 512) & 255;
273    
274 dpavlin 20 /* 64: Advanced PIO mode support. 0x02 = mode4, 0x01 = mode3 */
275     d->identify_struct[2 * 64 + 0] = 0x00;
276     d->identify_struct[2 * 64 + 1] = 0x03;
277    
278     /* 67, 68: PIO timing */
279     d->identify_struct[2 * 67 + 0] = 0;
280     d->identify_struct[2 * 67 + 1] = 120;
281     d->identify_struct[2 * 68 + 0] = 0;
282     d->identify_struct[2 * 68 + 1] = 120;
283 dpavlin 4 }
284    
285    
286     /*
287 dpavlin 14 * wdc__read():
288     */
289     void wdc__read(struct cpu *cpu, struct wdc_data *d)
290     {
291 dpavlin 20 #define MAX_SECTORS_PER_CHUNK 64
292     const int max_sectors_per_chunk = MAX_SECTORS_PER_CHUNK;
293     unsigned char buf[512 * MAX_SECTORS_PER_CHUNK];
294 dpavlin 14 int i, cyl = d->cyl_hi * 256+ d->cyl_lo;
295     int count = d->seccnt? d->seccnt : 256;
296     uint64_t offset = 512 * (d->sector - 1
297 dpavlin 32 + (int64_t)d->head * d->sectors_per_track[d->drive] +
298     (int64_t)d->heads[d->drive] * d->sectors_per_track[d->drive] * cyl);
299 dpavlin 14
300     #if 0
301     /* LBA: */
302     if (d->lba)
303     offset = 512 * (((d->head & 0xf) << 24) + (cyl << 8)
304     + d->sector);
305     printf("WDC read from offset %lli\n", (long long)offset);
306     #endif
307    
308     while (count > 0) {
309 dpavlin 18 int to_read = count > max_sectors_per_chunk?
310     max_sectors_per_chunk : count;
311    
312     /* TODO: result code from the read? */
313    
314     if (d->inbuf_head + 512 * to_read <= WDC_INBUF_SIZE) {
315     diskimage_access(cpu->machine, d->drive + d->base_drive,
316     DISKIMAGE_IDE, 0, offset,
317     d->inbuf + d->inbuf_head, 512 * to_read);
318     d->inbuf_head += 512 * to_read;
319     if (d->inbuf_head == WDC_INBUF_SIZE)
320     d->inbuf_head = 0;
321     } else {
322     diskimage_access(cpu->machine, d->drive + d->base_drive,
323     DISKIMAGE_IDE, 0, offset, buf, 512 * to_read);
324     for (i=0; i<512 * to_read; i++)
325     wdc_addtoinbuf(d, buf[i]);
326     }
327    
328     offset += 512 * to_read;
329     count -= to_read;
330 dpavlin 14 }
331    
332     d->delayed_interrupt = INT_DELAY;
333     }
334    
335    
336     /*
337     * wdc__write():
338     */
339     void wdc__write(struct cpu *cpu, struct wdc_data *d)
340     {
341     int cyl = d->cyl_hi * 256+ d->cyl_lo;
342     int count = d->seccnt? d->seccnt : 256;
343     uint64_t offset = 512 * (d->sector - 1
344 dpavlin 32 + (int64_t)d->head * d->sectors_per_track[d->drive] +
345     (int64_t)d->heads[d->drive] * d->sectors_per_track[d->drive] * cyl);
346 dpavlin 14 #if 0
347     /* LBA: */
348     if (d->lba)
349     offset = 512 * (((d->head & 0xf) << 24) +
350     (cyl << 8) + d->sector);
351     printf("WDC write to offset %lli\n", (long long)offset);
352     #endif
353    
354 dpavlin 20 d->write_in_progress = d->cur_command;
355 dpavlin 14 d->write_count = count;
356     d->write_offset = offset;
357    
358     /* TODO: result code? */
359     }
360    
361    
362     /*
363 dpavlin 4 * status_byte():
364 dpavlin 14 *
365     * Return a reasonable status byte corresponding to the controller's current
366     * state.
367 dpavlin 4 */
368     static int status_byte(struct wdc_data *d, struct cpu *cpu)
369     {
370     int odata = 0;
371 dpavlin 6 if (diskimage_exist(cpu->machine, d->drive + d->base_drive,
372     DISKIMAGE_IDE))
373 dpavlin 14 odata |= WDCS_DRDY | WDCS_DSC;
374 dpavlin 4 if (d->inbuf_head != d->inbuf_tail)
375     odata |= WDCS_DRQ;
376     if (d->write_in_progress)
377     odata |= WDCS_DRQ;
378     if (d->error)
379     odata |= WDCS_ERR;
380 dpavlin 20 if (d->atapi_cmd_in_progress && (d->atapi_phase & WDCS_DRQ)) {
381     odata |= WDCS_DRQ;
382     }
383 dpavlin 4 return odata;
384     }
385    
386    
387     /*
388     * dev_wdc_altstatus_access():
389     */
390 dpavlin 22 DEVICE_ACCESS(wdc_altstatus)
391 dpavlin 4 {
392     struct wdc_data *d = extra;
393     uint64_t idata = 0, odata = 0;
394    
395 dpavlin 18 idata = data[0];
396 dpavlin 4
397 dpavlin 20 /* Same as the normal status byte: */
398 dpavlin 4 odata = status_byte(d, cpu);
399    
400     if (writeflag==MEM_READ)
401     debug("[ wdc: read from ALTSTATUS: 0x%02x ]\n",
402     (int)odata);
403 dpavlin 20 else {
404 dpavlin 4 debug("[ wdc: write to ALT. CTRL: 0x%02x ]\n",
405     (int)idata);
406 dpavlin 20 if (idata & WDCTL_4BIT)
407     d->cur_command = COMMAND_RESET;
408     }
409 dpavlin 4
410     if (writeflag == MEM_READ)
411 dpavlin 18 data[0] = odata;
412 dpavlin 4
413     return 1;
414     }
415    
416    
417     /*
418 dpavlin 20 * wdc_command():
419     */
420     void wdc_command(struct cpu *cpu, struct wdc_data *d, int idata)
421     {
422 dpavlin 22 size_t i;
423 dpavlin 20
424     d->cur_command = idata;
425     d->atapi_cmd_in_progress = 0;
426     d->error = 0;
427    
428     /*
429     * Disk images that do not exist return an ABORT error. This also
430     * happens with CDROM images with the WDCC_IDENTIFY command; CDROM
431     * images must be detected with ATAPI_IDENTIFY_DEVICE instead.
432     *
433     * TODO: Is this correct/good behaviour?
434     */
435     if (!diskimage_exist(cpu->machine, d->drive + d->base_drive,
436     DISKIMAGE_IDE)) {
437     debug("[ wdc: command 0x%02x drive %i, but no disk image ]\n",
438     d->cur_command, d->drive + d->base_drive);
439     d->error |= WDCE_ABRT;
440     d->delayed_interrupt = INT_DELAY;
441     return;
442     }
443     if (diskimage_is_a_cdrom(cpu->machine, d->drive + d->base_drive,
444     DISKIMAGE_IDE) && d->cur_command == WDCC_IDENTIFY) {
445     debug("[ wdc: IDENTIFY drive %i, but it is an ATAPI "
446     "drive ]\n", d->drive + d->base_drive);
447     d->error |= WDCE_ABRT;
448     d->delayed_interrupt = INT_DELAY;
449     return;
450     }
451    
452     /* Handle the command: */
453     switch (d->cur_command) {
454    
455     case WDCC_READ:
456     case WDCC_READMULTI:
457     if (!quiet_mode)
458     debug("[ wdc: READ from drive %i, head %i, cyl %i, "
459     "sector %i, nsecs %i ]\n", d->drive, d->head,
460     d->cyl_hi*256+d->cyl_lo, d->sector, d->seccnt);
461     wdc__read(cpu, d);
462     break;
463    
464     case WDCC_WRITE:
465     case WDCC_WRITEMULTI:
466     if (!quiet_mode)
467     debug("[ wdc: WRITE to drive %i, head %i, cyl %i, "
468     "sector %i, nsecs %i ]\n", d->drive, d->head,
469     d->cyl_hi*256+d->cyl_lo, d->sector, d->seccnt);
470     wdc__write(cpu, d);
471     break;
472    
473     case WDCC_IDP: /* Initialize drive parameters */
474     debug("[ wdc: IDP drive %i (TODO) ]\n", d->drive);
475     /* TODO */
476     d->delayed_interrupt = INT_DELAY;
477     break;
478    
479     case SET_FEATURES:
480     debug("[ wdc: SET_FEATURES drive %i (TODO), feature 0x%02x ]\n",
481     d->drive, d->precomp);
482     /* TODO */
483     switch (d->precomp) {
484     case WDSF_SET_MODE:
485     debug("[ wdc: WDSF_SET_MODE drive %i, pio/dma flags "
486     "0x%02x ]\n", d->drive, d->seccnt);
487     break;
488     default:d->error |= WDCE_ABRT;
489     }
490     /* TODO: always interrupt? */
491     d->delayed_interrupt = INT_DELAY;
492     break;
493    
494     case WDCC_RECAL:
495     debug("[ wdc: RECAL drive %i ]\n", d->drive);
496     d->delayed_interrupt = INT_DELAY;
497     break;
498    
499     case WDCC_IDENTIFY:
500     case ATAPI_IDENTIFY_DEVICE:
501     debug("[ wdc: %sIDENTIFY drive %i ]\n", d->cur_command ==
502     ATAPI_IDENTIFY_DEVICE? "ATAPI " : "", d->drive);
503     wdc_initialize_identify_struct(cpu, d);
504     /* The IDENTIFY data is sent out in low/high byte order: */
505     for (i=0; i<sizeof(d->identify_struct); i+=2) {
506     wdc_addtoinbuf(d, d->identify_struct[i+1]);
507     wdc_addtoinbuf(d, d->identify_struct[i+0]);
508     }
509     d->delayed_interrupt = INT_DELAY;
510     break;
511    
512     case WDCC_IDLE_IMMED:
513     debug("[ wdc: IDLE_IMMED drive %i ]\n", d->drive);
514     /* TODO: interrupt here? */
515     d->delayed_interrupt = INT_DELAY;
516     break;
517    
518     case WDCC_SETMULTI:
519     debug("[ wdc: SETMULTI drive %i ]\n", d->drive);
520     /* TODO: interrupt here? */
521     d->delayed_interrupt = INT_DELAY;
522     break;
523    
524     case ATAPI_SOFT_RESET:
525     debug("[ wdc: ATAPI_SOFT_RESET drive %i ]\n", d->drive);
526     /* TODO: interrupt here? */
527     d->delayed_interrupt = INT_DELAY;
528     break;
529    
530     case ATAPI_PKT_CMD:
531     debug("[ wdc: ATAPI_PKT_CMD drive %i ]\n", d->drive);
532     /* TODO: interrupt here? */
533     /* d->delayed_interrupt = INT_DELAY; */
534     d->atapi_cmd_in_progress = 1;
535     d->atapi_phase = PHASE_CMDOUT;
536     break;
537    
538 dpavlin 22 case WDCC_DIAGNOSE:
539     debug("[ wdc: WDCC_DIAGNOSE drive %i: TODO ]\n", d->drive);
540     /* TODO: interrupt here? */
541     d->delayed_interrupt = INT_DELAY;
542     d->error = 1; /* No error? */
543     break;
544    
545 dpavlin 20 /* Unsupported commands, without warning: */
546     case WDCC_SEC_SET_PASSWORD:
547     case WDCC_SEC_UNLOCK:
548     case WDCC_SEC_ERASE_PREPARE:
549     case WDCC_SEC_ERASE_UNIT:
550     case WDCC_SEC_FREEZE_LOCK:
551     case WDCC_SEC_DISABLE_PASSWORD:
552     d->error |= WDCE_ABRT;
553     break;
554    
555     default:/* TODO */
556     d->error |= WDCE_ABRT;
557     fatal("[ wdc: WARNING! Unimplemented command 0x%02x (drive %i,"
558     " head %i, cyl %i, sector %i, nsecs %i) ]\n",
559     d->cur_command, d->drive, d->head, d->cyl_hi*256+d->cyl_lo,
560     d->sector, d->seccnt);
561     }
562     }
563    
564    
565     /*
566 dpavlin 4 * dev_wdc_access():
567     */
568 dpavlin 22 DEVICE_ACCESS(wdc)
569 dpavlin 4 {
570     struct wdc_data *d = extra;
571     uint64_t idata = 0, odata = 0;
572 dpavlin 14 int i;
573 dpavlin 4
574 dpavlin 22 relative_addr /= d->addr_mult;
575    
576 dpavlin 30 if (!d->io_enabled)
577     goto ret;
578    
579 dpavlin 18 if (writeflag == MEM_WRITE) {
580     if (relative_addr == wd_data)
581     idata = memory_readmax64(cpu, data, len);
582 dpavlin 20 else {
583     if (len != 1)
584     fatal("[ wdc: WARNING! non-8-bit access! ]\n");
585 dpavlin 18 idata = data[0];
586 dpavlin 20 }
587 dpavlin 18 }
588 dpavlin 4
589     switch (relative_addr) {
590    
591     case wd_data: /* 0: data */
592 dpavlin 18 if (writeflag == MEM_READ) {
593 dpavlin 22 odata = wdc_get_inbuf(d);
594 dpavlin 4
595 dpavlin 20 if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
596     if (len >= 2)
597     odata += (wdc_get_inbuf(d) << 8);
598     if (len == 4) {
599     odata += (wdc_get_inbuf(d) << 16);
600     odata += (wdc_get_inbuf(d) << 24);
601     }
602     } else {
603     if (len >= 2)
604     odata = (odata << 8) + wdc_get_inbuf(d);
605     if (len == 4) {
606     odata = (odata << 8) + wdc_get_inbuf(d);
607     odata = (odata << 8) + wdc_get_inbuf(d);
608     }
609 dpavlin 4 }
610    
611 dpavlin 20 if (d->data_debug) {
612 dpavlin 24 char *s = "0x%04"PRIx64" ]\n";
613 dpavlin 20 if (len == 1)
614 dpavlin 24 s = "0x%02"PRIx64" ]\n";
615 dpavlin 20 if (len == 4)
616 dpavlin 24 s = "0x%08"PRIx64" ]\n";
617 dpavlin 20 if (len == 8)
618 dpavlin 24 s = "0x%016"PRIx64" ]\n";
619 dpavlin 20 debug("[ wdc: read from DATA: ");
620 dpavlin 24 debug(s, (uint64_t) odata);
621 dpavlin 20 }
622    
623     if (d->atapi_cmd_in_progress) {
624     d->atapi_len -= len;
625     d->atapi_received += len;
626     if (d->atapi_len == 0) {
627     if (d->atapi_received < d->atapi_st->
628     data_in_len) {
629     d->atapi_phase = PHASE_DATAIN;
630     d->atapi_len = d->atapi_st->
631     data_in_len -
632     d->atapi_received;
633     if (d->atapi_len > 32768)
634     d->atapi_len = 0;
635     } else
636     d->atapi_phase =
637     PHASE_COMPLETED;
638     d->delayed_interrupt = INT_DELAY;
639     }
640     } else {
641 dpavlin 18 #if 0
642 dpavlin 20 if (d->inbuf_tail != d->inbuf_head)
643 dpavlin 18 #else
644 dpavlin 20 if (d->inbuf_tail != d->inbuf_head &&
645     ((d->inbuf_tail - d->inbuf_head) % 512)
646     == 0)
647 dpavlin 18 #endif
648 dpavlin 20 d->delayed_interrupt = INT_DELAY;
649     }
650 dpavlin 4 } else {
651     int inbuf_len;
652 dpavlin 20 if (d->data_debug) {
653 dpavlin 24 char *s = "0x%04"PRIx64" ]\n";
654 dpavlin 20 if (len == 1)
655 dpavlin 24 s = "0x%02"PRIx64" ]\n";
656 dpavlin 20 if (len == 4)
657 dpavlin 24 s = "0x%08"PRIx64" ]\n";
658 dpavlin 20 if (len == 8)
659 dpavlin 24 s = "0x%016"PRIx64" ]\n";
660 dpavlin 20 debug("[ wdc: write to DATA: ");
661 dpavlin 24 debug(s, (uint64_t) idata);
662 dpavlin 20 }
663     if (!d->write_in_progress &&
664     !d->atapi_cmd_in_progress) {
665 dpavlin 4 fatal("[ wdc: write to DATA, but not "
666     "expecting any? (len=%i): 0x%08lx ]\n",
667     (int)len, (long)idata);
668     }
669    
670 dpavlin 20 if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
671     switch (len) {
672     case 4: wdc_addtoinbuf(d, idata & 0xff);
673     wdc_addtoinbuf(d, (idata >> 8) & 0xff);
674     wdc_addtoinbuf(d, (idata >> 16) & 0xff);
675     wdc_addtoinbuf(d, (idata >> 24) & 0xff);
676     break;
677     case 2: wdc_addtoinbuf(d, idata & 0xff);
678     wdc_addtoinbuf(d, (idata >> 8) & 0xff);
679     break;
680     case 1: wdc_addtoinbuf(d, idata); break;
681     default:fatal("wdc: unimplemented write "
682     "len %i\n", len);
683     exit(1);
684     }
685     } else {
686     switch (len) {
687     case 4: wdc_addtoinbuf(d, (idata >> 24) & 0xff);
688     wdc_addtoinbuf(d, (idata >> 16) & 0xff);
689     wdc_addtoinbuf(d, (idata >> 8) & 0xff);
690     wdc_addtoinbuf(d, idata & 0xff);
691     break;
692     case 2: wdc_addtoinbuf(d, (idata >> 8) & 0xff);
693     wdc_addtoinbuf(d, idata & 0xff);
694     break;
695     case 1: wdc_addtoinbuf(d, idata); break;
696     default:fatal("wdc: unimplemented write "
697     "len %i\n", len);
698     exit(1);
699     }
700 dpavlin 4 }
701    
702     inbuf_len = d->inbuf_head - d->inbuf_tail;
703     while (inbuf_len < 0)
704     inbuf_len += WDC_INBUF_SIZE;
705    
706 dpavlin 20 if (d->atapi_cmd_in_progress && inbuf_len == 12) {
707     unsigned char *scsi_cmd = malloc(12);
708     int x = 0, res;
709    
710     if (d->atapi_st != NULL)
711     scsi_transfer_free(d->atapi_st);
712     d->atapi_st = scsi_transfer_alloc();
713    
714     debug("[ wdc: ATAPI command ]\n");
715    
716     while (inbuf_len > 0) {
717     scsi_cmd[x++] = wdc_get_inbuf(d);
718     inbuf_len --;
719     }
720    
721     d->atapi_st->cmd = scsi_cmd;
722     d->atapi_st->cmd_len = 12;
723    
724     if (scsi_cmd[0] == SCSIBLOCKCMD_READ_CAPACITY
725     || scsi_cmd[0] == SCSICMD_READ_10
726     || scsi_cmd[0] == SCSICMD_MODE_SENSE10)
727     d->atapi_st->cmd_len = 10;
728    
729     res = diskimage_scsicommand(cpu,
730     d->drive + d->base_drive, DISKIMAGE_IDE,
731     d->atapi_st);
732    
733     if (res == 0) {
734     fatal("WDC: ATAPI scsi error?\n");
735     exit(1);
736     }
737    
738     d->atapi_len = 0;
739     d->atapi_received = 0;
740    
741     if (res == 1) {
742     if (d->atapi_st->data_in != NULL) {
743     int i;
744     d->atapi_phase = PHASE_DATAIN;
745     d->atapi_len = d->atapi_st->
746     data_in_len;
747     for (i=0; i<d->atapi_len; i++)
748     wdc_addtoinbuf(d,
749     d->atapi_st->
750     data_in[i]);
751     if (d->atapi_len > 32768)
752     d->atapi_len = 32768;
753     } else {
754     d->atapi_phase =
755     PHASE_COMPLETED;
756     }
757     } else {
758     fatal("wdc atapi Dataout? TODO\n");
759     d->atapi_phase = PHASE_DATAOUT;
760     exit(1);
761     }
762    
763     d->delayed_interrupt = INT_DELAY;
764     }
765    
766     if (( d->write_in_progress == WDCC_WRITEMULTI &&
767     inbuf_len % (512 * d->write_count) == 0)
768     ||
769     ( d->write_in_progress == WDCC_WRITE &&
770     inbuf_len % 512 == 0) ) {
771     int count = (d->write_in_progress ==
772     WDCC_WRITEMULTI)? d->write_count : 1;
773 dpavlin 24 unsigned char *buf = malloc(512 * count);
774 dpavlin 18 unsigned char *b = buf;
775    
776 dpavlin 24 if (buf == NULL) {
777     fprintf(stderr, "out of memory\n");
778     exit(1);
779     }
780    
781 dpavlin 18 if (d->inbuf_tail+512*count <= WDC_INBUF_SIZE) {
782     b = d->inbuf + d->inbuf_tail;
783     d->inbuf_tail = (d->inbuf_tail + 512
784     * count) % WDC_INBUF_SIZE;
785     } else {
786     for (i=0; i<512 * count; i++)
787     buf[i] = wdc_get_inbuf(d);
788 dpavlin 4 }
789    
790     diskimage_access(cpu->machine,
791 dpavlin 6 d->drive + d->base_drive, DISKIMAGE_IDE, 1,
792 dpavlin 18 d->write_offset, b, 512 * count);
793 dpavlin 4
794 dpavlin 20 d->write_count -= count;
795     d->write_offset += 512 * count;
796 dpavlin 4
797     d->delayed_interrupt = INT_DELAY;
798    
799     if (d->write_count == 0)
800     d->write_in_progress = 0;
801 dpavlin 24
802     free(buf);
803 dpavlin 4 }
804     }
805     break;
806    
807     case wd_error: /* 1: error (r), precomp (w) */
808 dpavlin 20 if (writeflag == MEM_READ) {
809 dpavlin 4 odata = d->error;
810 dpavlin 22 debug("[ wdc: read from ERROR: 0x%02x ]\n", (int)odata);
811 dpavlin 4 /* TODO: is the error value cleared on read? */
812     d->error = 0;
813     } else {
814     d->precomp = idata;
815 dpavlin 14 debug("[ wdc: write to PRECOMP: 0x%02x ]\n",(int)idata);
816 dpavlin 4 }
817     break;
818    
819 dpavlin 20 case wd_seccnt: /* 2: sector count (or "ireason" for ATAPI) */
820     if (writeflag == MEM_READ) {
821 dpavlin 4 odata = d->seccnt;
822 dpavlin 20 if (d->atapi_cmd_in_progress) {
823     odata = d->atapi_phase & (WDCI_CMD | WDCI_IN);
824     }
825 dpavlin 14 debug("[ wdc: read from SECCNT: 0x%02x ]\n",(int)odata);
826 dpavlin 4 } else {
827     d->seccnt = idata;
828 dpavlin 14 debug("[ wdc: write to SECCNT: 0x%02x ]\n", (int)idata);
829 dpavlin 4 }
830     break;
831    
832     case wd_sector: /* 3: first sector */
833 dpavlin 20 if (writeflag == MEM_READ) {
834 dpavlin 4 odata = d->sector;
835 dpavlin 14 debug("[ wdc: read from SECTOR: 0x%02x ]\n",(int)odata);
836 dpavlin 4 } else {
837     d->sector = idata;
838 dpavlin 14 debug("[ wdc: write to SECTOR: 0x%02x ]\n", (int)idata);
839 dpavlin 4 }
840     break;
841    
842     case wd_cyl_lo: /* 4: cylinder low */
843 dpavlin 20 if (writeflag == MEM_READ) {
844 dpavlin 4 odata = d->cyl_lo;
845 dpavlin 20 if (d->cur_command == COMMAND_RESET &&
846     diskimage_is_a_cdrom(cpu->machine,
847     d->drive + d->base_drive, DISKIMAGE_IDE))
848     odata = 0x14;
849     if (d->atapi_cmd_in_progress) {
850     int x = d->atapi_len;
851     if (x > 32768)
852     x = 32768;
853     odata = x & 255;
854     }
855 dpavlin 14 debug("[ wdc: read from CYL_LO: 0x%02x ]\n",(int)odata);
856 dpavlin 4 } else {
857     d->cyl_lo = idata;
858 dpavlin 14 debug("[ wdc: write to CYL_LO: 0x%02x ]\n", (int)idata);
859 dpavlin 4 }
860     break;
861    
862 dpavlin 20 case wd_cyl_hi: /* 5: cylinder high */
863     if (writeflag == MEM_READ) {
864 dpavlin 4 odata = d->cyl_hi;
865 dpavlin 20 if (d->cur_command == COMMAND_RESET &&
866     diskimage_is_a_cdrom(cpu->machine,
867     d->drive + d->base_drive, DISKIMAGE_IDE))
868     odata = 0xeb;
869     if (d->atapi_cmd_in_progress) {
870     int x = d->atapi_len;
871     if (x > 32768)
872     x = 32768;
873     odata = (x >> 8) & 255;
874     }
875 dpavlin 14 debug("[ wdc: read from CYL_HI: 0x%02x ]\n",(int)odata);
876 dpavlin 4 } else {
877     d->cyl_hi = idata;
878 dpavlin 14 debug("[ wdc: write to CYL_HI: 0x%02x ]\n", (int)idata);
879 dpavlin 4 }
880     break;
881    
882     case wd_sdh: /* 6: sectorsize/drive/head */
883     if (writeflag==MEM_READ) {
884     odata = (d->sectorsize << 6) + (d->lba << 5) +
885     (d->drive << 4) + (d->head);
886     debug("[ wdc: read from SDH: 0x%02x (sectorsize %i,"
887     " lba=%i, drive %i, head %i) ]\n", (int)odata,
888     d->sectorsize, d->lba, d->drive, d->head);
889     } else {
890     d->sectorsize = (idata >> 6) & 3;
891     d->lba = (idata >> 5) & 1;
892     d->drive = (idata >> 4) & 1;
893     d->head = idata & 0xf;
894     debug("[ wdc: write to SDH: 0x%02x (sectorsize %i,"
895     " lba=%i, drive %i, head %i) ]\n", (int)idata,
896     d->sectorsize, d->lba, d->drive, d->head);
897     }
898     break;
899    
900     case wd_command: /* 7: command or status */
901     if (writeflag==MEM_READ) {
902     odata = status_byte(d, cpu);
903 dpavlin 6 if (!quiet_mode)
904     debug("[ wdc: read from STATUS: 0x%02x ]\n",
905 dpavlin 14 (int)odata);
906 dpavlin 4 cpu_interrupt_ack(cpu, d->irq_nr);
907 dpavlin 20 d->int_asserted = 0;
908 dpavlin 4 d->delayed_interrupt = 0;
909     } else {
910 dpavlin 14 debug("[ wdc: write to COMMAND: 0x%02x ]\n",(int)idata);
911 dpavlin 20 wdc_command(cpu, d, idata);
912 dpavlin 4 }
913     break;
914    
915     default:
916     if (writeflag==MEM_READ)
917     debug("[ wdc: read from 0x%02x ]\n",
918     (int)relative_addr);
919     else
920     debug("[ wdc: write to 0x%02x: 0x%02x ]\n",
921     (int)relative_addr, (int)idata);
922     }
923    
924 dpavlin 30
925 dpavlin 20 if (cpu->machine->machine_type != MACHINE_HPCMIPS &&
926     cpu->machine->machine_type != MACHINE_EVBMIPS &&
927 dpavlin 30 cpu->machine->machine_type != MACHINE_ALGOR &&
928 dpavlin 20 cpu->machine->machine_type != MACHINE_BEBOX)
929 dpavlin 18 dev_wdc_tick(cpu, extra);
930 dpavlin 4
931 dpavlin 30 ret:
932 dpavlin 18 if (writeflag == MEM_READ) {
933     if (relative_addr == wd_data)
934     memory_writemax64(cpu, data, len, odata);
935     else
936     data[0] = odata;
937     }
938    
939 dpavlin 4 return 1;
940     }
941    
942    
943 dpavlin 22 DEVINIT(wdc)
944 dpavlin 4 {
945     struct wdc_data *d;
946     uint64_t alt_status_addr;
947 dpavlin 18 int i, tick_shift = WDC_TICK_SHIFT;
948 dpavlin 4
949     d = malloc(sizeof(struct wdc_data));
950     if (d == NULL) {
951     fprintf(stderr, "out of memory\n");
952     exit(1);
953     }
954     memset(d, 0, sizeof(struct wdc_data));
955 dpavlin 22 d->irq_nr = devinit->irq_nr;
956     d->addr_mult = devinit->addr_mult;
957 dpavlin 20 d->data_debug = 1;
958 dpavlin 30 d->io_enabled = 1;
959 dpavlin 20
960     d->inbuf = zeroed_alloc(WDC_INBUF_SIZE);
961    
962 dpavlin 14 /* base_drive = 0 for the primary controller, 2 for the secondary. */
963     d->base_drive = 0;
964     if ((devinit->addr & 0xfff) == 0x170)
965     d->base_drive = 2;
966 dpavlin 4
967 dpavlin 14 alt_status_addr = devinit->addr + 0x206;
968    
969 dpavlin 22 /* Special hacks for individual machines: */
970     switch (devinit->machine->machine_type) {
971     case MACHINE_MACPPC:
972     alt_status_addr = devinit->addr + 0x160;
973     break;
974     case MACHINE_HPCMIPS:
975     /* TODO: Fix */
976     if (devinit->addr == 0x14000180)
977     alt_status_addr = 0x14000386;
978     break;
979     case MACHINE_IQ80321:
980     alt_status_addr = devinit->addr + 0x402;
981     break;
982     }
983 dpavlin 4
984 dpavlin 14 /* Get disk geometries: */
985     for (i=0; i<2; i++)
986     if (diskimage_exist(devinit->machine, d->base_drive +i,
987     DISKIMAGE_IDE))
988     diskimage_getchs(devinit->machine, d->base_drive + i,
989     DISKIMAGE_IDE, &d->cyls[i], &d->heads[i],
990     &d->sectors_per_track[i]);
991 dpavlin 4
992 dpavlin 14 memory_device_register(devinit->machine->memory, "wdc_altstatus",
993 dpavlin 20 alt_status_addr, 2, dev_wdc_altstatus_access, d, DM_DEFAULT, NULL);
994 dpavlin 14 memory_device_register(devinit->machine->memory, devinit->name,
995 dpavlin 22 devinit->addr, DEV_WDC_LENGTH * devinit->addr_mult, dev_wdc_access,
996     d, DM_DEFAULT, NULL);
997 dpavlin 14
998 dpavlin 20 if (devinit->machine->machine_type != MACHINE_HPCMIPS &&
999     devinit->machine->machine_type != MACHINE_EVBMIPS)
1000     tick_shift += 1;
1001 dpavlin 18
1002 dpavlin 14 machine_add_tickfunction(devinit->machine, dev_wdc_tick,
1003 dpavlin 24 d, tick_shift, 0.0);
1004 dpavlin 14
1005 dpavlin 30 devinit->return_ptr = d;
1006    
1007 dpavlin 14 return 1;
1008 dpavlin 4 }
1009    

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