/[gxemul]/trunk/src/devices/dev_vr41xx.c
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Contents of /trunk/src/devices/dev_vr41xx.c

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Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 16761 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 /*
2 * Copyright (C) 2004-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_vr41xx.c,v 1.37 2006/03/31 23:53:41 debug Exp $
29 *
30 * VR41xx (actually, VR4122 and VR4131) misc functions.
31 *
32 * This is just a big hack. TODO: Fix.
33 */
34
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38
39 #include "console.h"
40 #include "cpu.h"
41 #include "device.h"
42 #include "devices.h"
43 #include "machine.h"
44 #include "memory.h"
45 #include "misc.h"
46
47 #include "bcureg.h"
48 #include "vripreg.h"
49 #include "vrkiureg.h"
50
51
52 #define DEV_VR41XX_TICKSHIFT 15
53
54 /* #define debug fatal */
55
56
57 static void recalc_kiu_int_assert(struct cpu *cpu, struct vr41xx_data *d)
58 {
59 if (d->kiu_int_assert != 0)
60 cpu_interrupt(cpu, 8 + d->kiu_irq_nr);
61 else
62 cpu_interrupt_ack(cpu, 8 + d->kiu_irq_nr);
63 }
64
65
66 /*
67 * vr41xx_keytick():
68 */
69 static void vr41xx_keytick(struct cpu *cpu, struct vr41xx_data *d)
70 {
71 int keychange = 0;
72
73 /*
74 * Keyboard input:
75 *
76 * Hardcoded for MobilePro 780. (See NetBSD's hpckbdkeymap.h for
77 * info on other keyboard layouts. mobilepro780_keytrans is the
78 * one used here.)
79 *
80 * TODO: Make this work with "any" keyboard layout.
81 *
82 * (Even MobilePro 770 seems to be different? Hm. TODO)
83 *
84 * ofs 0:
85 * 8000='o' 4000='.' 2000=DOWN 1000=UP
86 * 800=';' 400=''' 200='[' 100=?
87 * 80='l' 40=CR 20=RIGHT 10=LEFT
88 * 8='/' 4='\' 2=']' 1=SPACE
89 * ofs 2:
90 * 8000='a' 4000='s' 2000='d' 1000='f'
91 * 800='`' 400='-' 200='=' 100=?
92 * 80='z' 40='x' 20='c' 10='v'
93 * 8=? 4=? 2=?
94 * ofs 4:
95 * 8000='9' 4000='0' 2000=? 1000=?
96 * 800='b' 400='n' 200='m' 100=','
97 * 80='q' 40='w' 20='e' 10='r'
98 * 8='5' 4='6' 2='7' 1='8'
99 * ofs 6:
100 * 8000=ESC 4000=DEL 2000=CAPS 1000=?
101 * 800='t' 400='y' 200='u' 100='i'
102 * 80='1' 40='2' 20='3' 10='4'
103 * 8='g' 4='h' 2='j' 1='k'
104 * ofs 8:
105 * 200=ALT_L
106 * 80= 40=TAB 20='p' 10=BS
107 * 8= 4= 2= 1=ALT_R
108 * ofs a:
109 * 800=SHIFT 4=CTRL
110 *
111 *
112 * The following are for the IBM WorkPad Z50:
113 * (Not yet implemented, TODO)
114 *
115 * 00 f1 f3 f5 f7 f9 - - f11
116 * 08 f2 f4 f6 f8 f10 - - f12
117 * 10 ' [ - 0 p ; up /
118 * 18 - - - 9 o l . -
119 * 20 left ] = 8 i k , -
120 * 28 h y 6 7 u j m n
121 * 30 - bs num del - \ ent sp
122 * 38 g t 5 4 r f v b
123 * 40 - - - 3 e d c right
124 * 48 - - - 2 w s x down
125 * 50 esc tab ~ 1 q a z -
126 * 58 menu Ls Lc Rc La Ra Rs -
127 */
128
129 if (d->d0 != 0 || d->d1 != 0 || d->d2 != 0 ||
130 d->d3 != 0 || d->d4 != 0 || d->d5 != 0)
131 keychange = 1;
132
133 /* Release all keys: */
134 if (!d->dont_clear_next) {
135 d->d0 = d->d1 = d->d2 = d->d3 = d->d4 = d->d5 = 0;
136 } else
137 d->dont_clear_next = 0;
138
139 if (console_charavail(d->kiu_console_handle)) {
140 char ch = console_readchar(d->kiu_console_handle);
141
142 if (d->escape_state > 0) {
143 switch (d->escape_state) {
144 case 1: /* expecting a [ */
145 d->escape_state = 0;
146 if (ch == '[')
147 d->escape_state = 2;
148 break;
149 case 2: /* cursor keys etc: */
150 switch (ch) {
151 case 'A': d->d0 = 0x1000; break;
152 case 'B': d->d0 = 0x2000; break;
153 case 'C': d->d0 = 0x20; break;
154 case 'D': d->d0 = 0x10; break;
155 default: fatal("[ vr41xx kiu: "
156 "unimplemented escape 0x%02 ]\n", ch);
157 }
158 d->escape_state = 0;
159 }
160 } else switch (ch) {
161 case '+': console_makeavail(d->kiu_console_handle, '=');
162 d->d5 = 0x800; break;
163 case '_': console_makeavail(d->kiu_console_handle, '-');
164 d->d5 = 0x800; break;
165 case '<': console_makeavail(d->kiu_console_handle, ',');
166 d->d5 = 0x800; break;
167 case '>': console_makeavail(d->kiu_console_handle, '.');
168 d->d5 = 0x800; break;
169 case '{': console_makeavail(d->kiu_console_handle, '[');
170 d->d5 = 0x800; break;
171 case '}': console_makeavail(d->kiu_console_handle, ']');
172 d->d5 = 0x800; break;
173 case ':': console_makeavail(d->kiu_console_handle, ';');
174 d->d5 = 0x800; break;
175 case '"': console_makeavail(d->kiu_console_handle, '\'');
176 d->d5 = 0x800; break;
177 case '|': console_makeavail(d->kiu_console_handle, '\\');
178 d->d5 = 0x800; break;
179 case '?': console_makeavail(d->kiu_console_handle, '/');
180 d->d5 = 0x800; break;
181
182 case '!': console_makeavail(d->kiu_console_handle, '1');
183 d->d5 = 0x800; break;
184 case '@': console_makeavail(d->kiu_console_handle, '2');
185 d->d5 = 0x800; break;
186 case '#': console_makeavail(d->kiu_console_handle, '3');
187 d->d5 = 0x800; break;
188 case '$': console_makeavail(d->kiu_console_handle, '4');
189 d->d5 = 0x800; break;
190 case '%': console_makeavail(d->kiu_console_handle, '5');
191 d->d5 = 0x800; break;
192 case '^': console_makeavail(d->kiu_console_handle, '6');
193 d->d5 = 0x800; break;
194 case '&': console_makeavail(d->kiu_console_handle, '7');
195 d->d5 = 0x800; break;
196 case '*': console_makeavail(d->kiu_console_handle, '8');
197 d->d5 = 0x800; break;
198 case '(': console_makeavail(d->kiu_console_handle, '9');
199 d->d5 = 0x800; break;
200 case ')': console_makeavail(d->kiu_console_handle, '0');
201 d->d5 = 0x800; break;
202
203 case '1': d->d3 = 0x80; break;
204 case '2': d->d3 = 0x40; break;
205 case '3': d->d3 = 0x20; break;
206 case '4': d->d3 = 0x10; break;
207 case '5': d->d2 = 0x08; break;
208 case '6': d->d2 = 0x04; break;
209 case '7': d->d2 = 0x02; break;
210 case '8': d->d2 = 0x01; break;
211 case '9': d->d2 = 0x8000; break;
212 case '0': d->d2 = 0x4000; break;
213
214 case ';': d->d0 = 0x800; break;
215 case '\'': d->d0 = 0x400; break;
216 case '[': d->d0 = 0x200; break;
217 case '/': d->d0 = 0x8; break;
218 case '\\': d->d0 = 0x4; break;
219 case ']': d->d0 = 0x2; break;
220
221 case 'a': d->d1 = 0x8000; break;
222 case 'b': d->d2 = 0x800; break;
223 case 'c': d->d1 = 0x20; break;
224 case 'd': d->d1 = 0x2000; break;
225 case 'e': d->d2 = 0x20; break;
226 case 'f': d->d1 = 0x1000; break;
227 case 'g': d->d3 = 0x8; break;
228 case 'h': d->d3 = 0x4; break;
229 case 'i': d->d3 = 0x100; break;
230 case 'j': d->d3 = 0x2; break;
231 case 'k': d->d3 = 0x1; break;
232 case 'l': d->d0 = 0x80; break;
233 case 'm': d->d2 = 0x200; break;
234 case 'n': d->d2 = 0x400; break;
235 case 'o': d->d0 = 0x8000; break;
236 case 'p': d->d4 = 0x20; break;
237 case 'q': d->d2 = 0x80; break;
238 case 'r': d->d2 = 0x10; break;
239 case 's': d->d1 = 0x4000; break;
240 case 't': d->d3 = 0x800; break;
241 case 'u': d->d3 = 0x200; break;
242 case 'v': d->d1 = 0x10; break;
243 case 'w': d->d2 = 0x40; break;
244 case 'x': d->d1 = 0x40; break;
245 case 'y': d->d3 = 0x400; break;
246 case 'z': d->d1 = 0x80; break;
247
248 case ',': d->d2 = 0x100; break;
249 case '.': d->d0 = 0x4000; break;
250 case '-': d->d1 = 0x400; break;
251 case '=': d->d1 = 0x200; break;
252
253 case '\r':
254 case '\n': d->d0 = 0x40; break;
255 case ' ': d->d0 = 0x01; break;
256 case '\b': d->d4 = 0x10; break;
257
258 case 27: d->escape_state = 1; break;
259
260 default:
261 /* Shifted: */
262 if (ch >= 'A' && ch <= 'Z') {
263 console_makeavail(d->kiu_console_handle,
264 ch + 32);
265 d->d5 = 0x800;
266 d->dont_clear_next = 1;
267 break;
268 }
269
270 /* CTRLed: */
271 if (ch >= 1 && ch <= 26) {
272 console_makeavail(d->kiu_console_handle,
273 ch + 96);
274 d->d5 = 0x4;
275 d->dont_clear_next = 1;
276 break;
277 }
278 }
279
280 if (d->escape_state == 0)
281 keychange = 1;
282 }
283
284 if (keychange) {
285 /* 4=lost data, 2=data complete, 1=key input detected */
286 d->kiu_int_assert |= 3;
287 recalc_kiu_int_assert(cpu, d);
288 }
289 }
290
291
292 /*
293 * dev_vr41xx_tick():
294 */
295 void dev_vr41xx_tick(struct cpu *cpu, void *extra)
296 {
297 struct vr41xx_data *d = extra;
298
299 /*
300 * UGLY! TODO: fix this.
301 *
302 * Interrupts should be triggered if the corresponding unit (for
303 * example the RTC unit) is activated.
304 */
305 {
306 static unsigned int x = 0;
307 x++;
308
309 if (x > 100 && (x&3)==0) {
310 if (d->cpumodel == 4121 || d->cpumodel == 4181)
311 cpu_interrupt(cpu, 3);
312 else
313 cpu_interrupt(cpu, 8 + VRIP_INTR_ETIMER);
314 }
315 }
316
317 if (cpu->machine->use_x11)
318 vr41xx_keytick(cpu, d);
319 }
320
321
322 /*
323 * vr41xx_kiu():
324 *
325 * Keyboard Interface Unit. Return value is "odata".
326 * (See NetBSD's vrkiu.c for more info.)
327 */
328 static uint64_t vr41xx_kiu(struct cpu *cpu, int ofs, uint64_t idata,
329 int writeflag, struct vr41xx_data *d)
330 {
331 uint64_t odata = 0;
332
333 switch (ofs) {
334 case KIUDAT0:
335 odata = d->d0; break;
336 case KIUDAT1:
337 odata = d->d1; break;
338 case KIUDAT2:
339 odata = d->d2; break;
340 case KIUDAT3:
341 odata = d->d3; break;
342 case KIUDAT4:
343 odata = d->d4; break;
344 case KIUDAT5:
345 odata = d->d5; break;
346 case KIUSCANREP:
347 if (writeflag == MEM_WRITE) {
348 debug("[ vr41xx KIU: setting KIUSCANREP to 0x%04x ]\n",
349 (int)idata);
350 /* TODO */
351 } else
352 fatal("[ vr41xx KIU: unimplemented read from "
353 "KIUSCANREP ]\n");
354 break;
355 case KIUSCANS:
356 if (writeflag == MEM_WRITE) {
357 debug("[ vr41xx KIU: write to KIUSCANS: 0x%04x: TODO"
358 " ]\n", (int)idata);
359 /* TODO */
360 } else
361 debug("[ vr41xx KIU: unimplemented read from "
362 "KIUSCANS ]\n");
363 break;
364 case KIUINT:
365 /* Interrupt. A wild guess: zero-on-write */
366 if (writeflag == MEM_WRITE) {
367 d->kiu_int_assert &= ~idata;
368 } else {
369 odata = d->kiu_int_assert;
370 }
371 recalc_kiu_int_assert(cpu, d);
372 break;
373 case KIURST:
374 /* Reset. */
375 break;
376 default:
377 if (writeflag == MEM_WRITE)
378 debug("[ vr41xx KIU: unimplemented write to offset "
379 "0x%x, data=0x%016"PRIx64" ]\n", ofs,
380 (uint64_t) idata);
381 else
382 debug("[ vr41xx KIU: unimplemented read from offset "
383 "0x%x ]\n", ofs);
384 }
385
386 return odata;
387 }
388
389
390 /*
391 * dev_vr41xx_access():
392 */
393 DEVICE_ACCESS(vr41xx)
394 {
395 struct vr41xx_data *d = (struct vr41xx_data *) extra;
396 uint64_t idata = 0, odata = 0;
397 int regnr;
398 int revision = 0;
399
400 if (writeflag == MEM_WRITE)
401 idata = memory_readmax64(cpu, data, len);
402
403 regnr = relative_addr / sizeof(uint64_t);
404
405 /* KIU ("Keyboard Interface Unit") is handled separately. */
406 if (relative_addr >= d->kiu_offset &&
407 relative_addr < d->kiu_offset + 0x20) {
408 odata = vr41xx_kiu(cpu, relative_addr - d->kiu_offset,
409 idata, writeflag, d);
410 goto ret;
411 }
412
413 /* TODO: Maybe these should be handled separately as well? */
414
415 switch (relative_addr) {
416 /* BCU: 0x00 .. 0x1c */
417 case BCUREVID_REG_W: /* 0x010 */
418 case BCU81REVID_REG_W: /* 0x014 */
419 /*
420 * TODO? Linux seems to read 0x14. The lowest bits are
421 * a divisor for PClock, bits 8 and up seem to be a
422 * divisor for VTClock (relative to PClock?)...
423 */
424 switch (d->cpumodel) {
425 case 4131: revision = BCUREVID_RID_4131; break;
426 case 4122: revision = BCUREVID_RID_4122; break;
427 case 4121: revision = BCUREVID_RID_4121; break;
428 case 4111: revision = BCUREVID_RID_4111; break;
429 case 4102: revision = BCUREVID_RID_4102; break;
430 case 4101: revision = BCUREVID_RID_4101; break;
431 case 4181: revision = BCUREVID_RID_4181; break;
432 }
433 odata = (revision << BCUREVID_RIDSHFT) | 0x020c;
434 break;
435 case BCU81CLKSPEED_REG_W: /* 0x018 */
436 /*
437 * TODO: Implement this for ALL cpu types:
438 */
439 odata = BCUCLKSPEED_DIVT4 << BCUCLKSPEED_DIVTSHFT;
440 break;
441
442 /* DMAAU: 0x20 .. 0x3c */
443
444 /* DCU: 0x40 .. 0x5c */
445
446 /* CMU: 0x60 .. 0x7c */
447
448 /* ICU: 0x80 .. 0xbc */
449 case 0x80: /* Level 1 system interrupt reg 1... */
450 if (writeflag == MEM_READ)
451 odata = d->sysint1;
452 else {
453 /* TODO: clear-on-write-one? */
454 d->sysint1 &= ~idata;
455 d->sysint1 &= 0xffff;
456 }
457 break;
458 case 0x88:
459 if (writeflag == MEM_READ)
460 odata = d->giuint;
461 else
462 d->giuint &= ~idata;
463 break;
464 case 0x8c:
465 if (writeflag == MEM_READ)
466 odata = d->msysint1;
467 else
468 d->msysint1 = idata;
469 break;
470 case 0x94:
471 if (writeflag == MEM_READ)
472 odata = d->giumask;
473 else
474 d->giumask = idata;
475 break;
476 case 0xa0: /* Level 1 system interrupt reg 2... */
477 if (writeflag == MEM_READ)
478 odata = d->sysint2;
479 else {
480 /* TODO: clear-on-write-one? */
481 d->sysint2 &= ~idata;
482 d->sysint2 &= 0xffff;
483 }
484 break;
485 case 0xa6:
486 if (writeflag == MEM_READ)
487 odata = d->msysint2;
488 else
489 d->msysint2 = idata;
490 break;
491
492 /* PMU: 0xc0 .. 0xfc */
493 /* RTC: 0x100 .. ? */
494
495 case 0x108:
496 if (writeflag == MEM_READ)
497 odata = d->giuint;
498 else
499 d->giuint &= ~idata;
500 break;
501 /* case 0x10a:
502 "High" part of GIU?
503 break;
504 */
505
506 case 0x13e: /* on 4181? */
507 /* RTC interrupt register... */
508 /* Ack. timer interrupts? */
509 cpu_interrupt_ack(cpu, 8 + VRIP_INTR_ETIMER);
510 break;
511
512 case 0x1de: /* on 4121? */
513 /* RTC interrupt register... */
514 /* Ack. timer interrupts? */
515 cpu_interrupt_ack(cpu, 3);
516 break;
517
518 default:
519 if (writeflag == MEM_WRITE)
520 debug("[ vr41xx: unimplemented write to address "
521 "0x%"PRIx64", data=0x%016"PRIx64" ]\n",
522 (uint64_t) relative_addr, (uint64_t) idata);
523 else
524 debug("[ vr41xx: unimplemented read from address "
525 "0x%"PRIx64" ]\n", (uint64_t) relative_addr);
526 }
527
528 ret:
529 /* Recalculate interrupt assertions: */
530 cpu_interrupt_ack(cpu, 8 + 31); /* TODO: hopefully nothing
531 useful at irq 15 in
532 sysint2 */
533
534 if (writeflag == MEM_READ)
535 memory_writemax64(cpu, data, len, odata);
536
537 return 1;
538 }
539
540
541 /*
542 * dev_vr41xx_init():
543 */
544 struct vr41xx_data *dev_vr41xx_init(struct machine *machine,
545 struct memory *mem, int cpumodel)
546 {
547 uint64_t baseaddr = 0;
548 char tmps[100];
549 struct vr41xx_data *d = malloc(sizeof(struct vr41xx_data));
550
551 if (d == NULL) {
552 fprintf(stderr, "out of memory\n");
553 exit(1);
554 }
555 memset(d, 0, sizeof(struct vr41xx_data));
556
557 d->cpumodel = cpumodel;
558
559 /* TODO: VRC4173 has the KIU at offset 0x100? */
560 d->kiu_offset = 0x180;
561 d->kiu_console_handle = console_start_slave_inputonly(
562 machine, "kiu", 1);
563 d->kiu_irq_nr = VRIP_INTR_KIU;
564
565 switch (cpumodel) {
566 case 4101:
567 case 4102:
568 case 4111:
569 case 4121:
570 baseaddr = 0xb000000;
571 break;
572 case 4181:
573 baseaddr = 0xa000000;
574 dev_ram_init(machine, 0xb000000, 0x1000000, DEV_RAM_MIRROR,
575 0xa000000);
576 break;
577 case 4122:
578 case 4131:
579 baseaddr = 0xf000000;
580 break;
581 default:
582 printf("Unimplemented VR cpu model\n");
583 exit(1);
584 }
585
586 memory_device_register(mem, "vr41xx", baseaddr, DEV_VR41XX_LENGTH,
587 dev_vr41xx_access, (void *)d, DM_DEFAULT, NULL);
588
589 /*
590 * TODO: Find out which controllers are at which addresses on
591 * which chips.
592 */
593 if (cpumodel == 4131) {
594 snprintf(tmps, sizeof(tmps), "ns16550 irq=%i addr=0x%"PRIx64" "
595 "name2=siu", 8+VRIP_INTR_SIU, (uint64_t) (baseaddr+0x800));
596 device_add(machine, tmps);
597 } else {
598 /* This is used by Linux and NetBSD: */
599 snprintf(tmps, sizeof(tmps), "ns16550 irq=%i addr=0x%x "
600 "name2=serial", 8+VRIP_INTR_SIU, 0xc000000);
601 device_add(machine, tmps);
602 }
603
604 /* Hm... maybe this should not be here. TODO */
605 device_add(machine, "pcic addr=0x140003e0");
606
607 machine_add_tickfunction(machine, dev_vr41xx_tick, d,
608 DEV_VR41XX_TICKSHIFT, 0.0);
609
610 /* Some machines (?) use ISA space at 0x15000000 instead of
611 0x14000000, eg IBM WorkPad Z50. */
612 dev_ram_init(machine, 0x15000000, 0x1000000, DEV_RAM_MIRROR,
613 0x14000000);
614
615 return d;
616 }
617

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