/[gxemul]/trunk/src/devices/dev_vr41xx.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Annotation of /trunk/src/devices/dev_vr41xx.c

Parent Directory Parent Directory | Revision Log Revision Log


Revision 32 - (hide annotations)
Mon Oct 8 16:20:58 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 17930 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 dpavlin 4 /*
2 dpavlin 22 * Copyright (C) 2004-2006 Anders Gavare. All rights reserved.
3 dpavlin 4 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 32 * $Id: dev_vr41xx.c,v 1.41 2006/10/02 09:26:53 debug Exp $
29 dpavlin 4 *
30     * VR41xx (actually, VR4122 and VR4131) misc functions.
31     *
32     * This is just a big hack. TODO: Fix.
33     */
34    
35     #include <stdio.h>
36     #include <stdlib.h>
37     #include <string.h>
38    
39     #include "console.h"
40     #include "cpu.h"
41     #include "device.h"
42     #include "devices.h"
43     #include "machine.h"
44     #include "memory.h"
45     #include "misc.h"
46 dpavlin 32 #include "timer.h"
47 dpavlin 4
48     #include "bcureg.h"
49     #include "vripreg.h"
50     #include "vrkiureg.h"
51 dpavlin 32 #include "vr_rtcreg.h"
52 dpavlin 4
53    
54 dpavlin 32 #define DEV_VR41XX_TICKSHIFT 14
55 dpavlin 4
56     /* #define debug fatal */
57    
58    
59     static void recalc_kiu_int_assert(struct cpu *cpu, struct vr41xx_data *d)
60     {
61     if (d->kiu_int_assert != 0)
62     cpu_interrupt(cpu, 8 + d->kiu_irq_nr);
63     else
64     cpu_interrupt_ack(cpu, 8 + d->kiu_irq_nr);
65     }
66    
67    
68     /*
69     * vr41xx_keytick():
70     */
71     static void vr41xx_keytick(struct cpu *cpu, struct vr41xx_data *d)
72     {
73     int keychange = 0;
74    
75     /*
76     * Keyboard input:
77     *
78 dpavlin 32 * Hardcoded for MobilePro. (See NetBSD's hpckbdkeymap.h for
79 dpavlin 4 * info on other keyboard layouts. mobilepro780_keytrans is the
80     * one used here.)
81     *
82     * TODO: Make this work with "any" keyboard layout.
83     *
84     * ofs 0:
85     * 8000='o' 4000='.' 2000=DOWN 1000=UP
86     * 800=';' 400=''' 200='[' 100=?
87     * 80='l' 40=CR 20=RIGHT 10=LEFT
88     * 8='/' 4='\' 2=']' 1=SPACE
89     * ofs 2:
90     * 8000='a' 4000='s' 2000='d' 1000='f'
91     * 800='`' 400='-' 200='=' 100=?
92     * 80='z' 40='x' 20='c' 10='v'
93     * 8=? 4=? 2=?
94     * ofs 4:
95     * 8000='9' 4000='0' 2000=? 1000=?
96     * 800='b' 400='n' 200='m' 100=','
97     * 80='q' 40='w' 20='e' 10='r'
98     * 8='5' 4='6' 2='7' 1='8'
99     * ofs 6:
100     * 8000=ESC 4000=DEL 2000=CAPS 1000=?
101     * 800='t' 400='y' 200='u' 100='i'
102     * 80='1' 40='2' 20='3' 10='4'
103     * 8='g' 4='h' 2='j' 1='k'
104     * ofs 8:
105     * 200=ALT_L
106     * 80= 40=TAB 20='p' 10=BS
107     * 8= 4= 2= 1=ALT_R
108     * ofs a:
109     * 800=SHIFT 4=CTRL
110     *
111     *
112     * The following are for the IBM WorkPad Z50:
113     * (Not yet implemented, TODO)
114     *
115     * 00 f1 f3 f5 f7 f9 - - f11
116     * 08 f2 f4 f6 f8 f10 - - f12
117     * 10 ' [ - 0 p ; up /
118     * 18 - - - 9 o l . -
119     * 20 left ] = 8 i k , -
120     * 28 h y 6 7 u j m n
121     * 30 - bs num del - \ ent sp
122     * 38 g t 5 4 r f v b
123     * 40 - - - 3 e d c right
124     * 48 - - - 2 w s x down
125     * 50 esc tab ~ 1 q a z -
126     * 58 menu Ls Lc Rc La Ra Rs -
127     */
128    
129     if (d->d0 != 0 || d->d1 != 0 || d->d2 != 0 ||
130     d->d3 != 0 || d->d4 != 0 || d->d5 != 0)
131     keychange = 1;
132    
133     /* Release all keys: */
134     if (!d->dont_clear_next) {
135     d->d0 = d->d1 = d->d2 = d->d3 = d->d4 = d->d5 = 0;
136     } else
137     d->dont_clear_next = 0;
138    
139     if (console_charavail(d->kiu_console_handle)) {
140     char ch = console_readchar(d->kiu_console_handle);
141    
142     if (d->escape_state > 0) {
143     switch (d->escape_state) {
144     case 1: /* expecting a [ */
145     d->escape_state = 0;
146     if (ch == '[')
147     d->escape_state = 2;
148     break;
149     case 2: /* cursor keys etc: */
150 dpavlin 32 /* Ugly hack for Mobilepro770: */
151     if (cpu->machine->machine_subtype ==
152     MACHINE_HPCMIPS_NEC_MOBILEPRO_770) {
153     switch (ch) {
154     case 'A': d->d0 = 0x2000; break;
155     case 'B': d->d0 = 0x20; break;
156     case 'C': d->d0 = 0x1000; break;
157     case 'D': d->d0 = 0x10; break;
158     default: fatal("[ vr41xx kiu: unimpl"
159     "emented escape 0x%02 ]\n", ch);
160     }
161     } else {
162     switch (ch) {
163     case 'A': d->d0 = 0x1000; break;
164     case 'B': d->d0 = 0x2000; break;
165     case 'C': d->d0 = 0x20; break;
166     case 'D': d->d0 = 0x10; break;
167     default: fatal("[ vr41xx kiu: unimpl"
168     "emented escape 0x%02 ]\n", ch);
169     }
170 dpavlin 4 }
171     d->escape_state = 0;
172     }
173     } else switch (ch) {
174     case '+': console_makeavail(d->kiu_console_handle, '=');
175     d->d5 = 0x800; break;
176     case '_': console_makeavail(d->kiu_console_handle, '-');
177     d->d5 = 0x800; break;
178     case '<': console_makeavail(d->kiu_console_handle, ',');
179     d->d5 = 0x800; break;
180     case '>': console_makeavail(d->kiu_console_handle, '.');
181     d->d5 = 0x800; break;
182     case '{': console_makeavail(d->kiu_console_handle, '[');
183     d->d5 = 0x800; break;
184     case '}': console_makeavail(d->kiu_console_handle, ']');
185     d->d5 = 0x800; break;
186     case ':': console_makeavail(d->kiu_console_handle, ';');
187     d->d5 = 0x800; break;
188     case '"': console_makeavail(d->kiu_console_handle, '\'');
189     d->d5 = 0x800; break;
190     case '|': console_makeavail(d->kiu_console_handle, '\\');
191     d->d5 = 0x800; break;
192     case '?': console_makeavail(d->kiu_console_handle, '/');
193     d->d5 = 0x800; break;
194    
195     case '!': console_makeavail(d->kiu_console_handle, '1');
196     d->d5 = 0x800; break;
197     case '@': console_makeavail(d->kiu_console_handle, '2');
198     d->d5 = 0x800; break;
199     case '#': console_makeavail(d->kiu_console_handle, '3');
200     d->d5 = 0x800; break;
201     case '$': console_makeavail(d->kiu_console_handle, '4');
202     d->d5 = 0x800; break;
203     case '%': console_makeavail(d->kiu_console_handle, '5');
204     d->d5 = 0x800; break;
205     case '^': console_makeavail(d->kiu_console_handle, '6');
206     d->d5 = 0x800; break;
207     case '&': console_makeavail(d->kiu_console_handle, '7');
208     d->d5 = 0x800; break;
209     case '*': console_makeavail(d->kiu_console_handle, '8');
210     d->d5 = 0x800; break;
211     case '(': console_makeavail(d->kiu_console_handle, '9');
212     d->d5 = 0x800; break;
213     case ')': console_makeavail(d->kiu_console_handle, '0');
214     d->d5 = 0x800; break;
215    
216     case '1': d->d3 = 0x80; break;
217     case '2': d->d3 = 0x40; break;
218     case '3': d->d3 = 0x20; break;
219     case '4': d->d3 = 0x10; break;
220     case '5': d->d2 = 0x08; break;
221     case '6': d->d2 = 0x04; break;
222     case '7': d->d2 = 0x02; break;
223     case '8': d->d2 = 0x01; break;
224     case '9': d->d2 = 0x8000; break;
225     case '0': d->d2 = 0x4000; break;
226    
227     case ';': d->d0 = 0x800; break;
228     case '\'': d->d0 = 0x400; break;
229     case '[': d->d0 = 0x200; break;
230     case '/': d->d0 = 0x8; break;
231     case '\\': d->d0 = 0x4; break;
232     case ']': d->d0 = 0x2; break;
233    
234     case 'a': d->d1 = 0x8000; break;
235     case 'b': d->d2 = 0x800; break;
236     case 'c': d->d1 = 0x20; break;
237     case 'd': d->d1 = 0x2000; break;
238     case 'e': d->d2 = 0x20; break;
239     case 'f': d->d1 = 0x1000; break;
240     case 'g': d->d3 = 0x8; break;
241     case 'h': d->d3 = 0x4; break;
242     case 'i': d->d3 = 0x100; break;
243     case 'j': d->d3 = 0x2; break;
244     case 'k': d->d3 = 0x1; break;
245     case 'l': d->d0 = 0x80; break;
246     case 'm': d->d2 = 0x200; break;
247     case 'n': d->d2 = 0x400; break;
248     case 'o': d->d0 = 0x8000; break;
249     case 'p': d->d4 = 0x20; break;
250     case 'q': d->d2 = 0x80; break;
251     case 'r': d->d2 = 0x10; break;
252     case 's': d->d1 = 0x4000; break;
253     case 't': d->d3 = 0x800; break;
254     case 'u': d->d3 = 0x200; break;
255     case 'v': d->d1 = 0x10; break;
256     case 'w': d->d2 = 0x40; break;
257     case 'x': d->d1 = 0x40; break;
258     case 'y': d->d3 = 0x400; break;
259     case 'z': d->d1 = 0x80; break;
260    
261     case ',': d->d2 = 0x100; break;
262     case '.': d->d0 = 0x4000; break;
263     case '-': d->d1 = 0x400; break;
264     case '=': d->d1 = 0x200; break;
265    
266     case '\r':
267     case '\n': d->d0 = 0x40; break;
268     case ' ': d->d0 = 0x01; break;
269     case '\b': d->d4 = 0x10; break;
270    
271     case 27: d->escape_state = 1; break;
272    
273     default:
274     /* Shifted: */
275     if (ch >= 'A' && ch <= 'Z') {
276     console_makeavail(d->kiu_console_handle,
277     ch + 32);
278     d->d5 = 0x800;
279     d->dont_clear_next = 1;
280     break;
281     }
282    
283     /* CTRLed: */
284     if (ch >= 1 && ch <= 26) {
285     console_makeavail(d->kiu_console_handle,
286     ch + 96);
287     d->d5 = 0x4;
288     d->dont_clear_next = 1;
289     break;
290     }
291     }
292    
293     if (d->escape_state == 0)
294     keychange = 1;
295     }
296    
297     if (keychange) {
298     /* 4=lost data, 2=data complete, 1=key input detected */
299     d->kiu_int_assert |= 3;
300     recalc_kiu_int_assert(cpu, d);
301     }
302     }
303    
304    
305 dpavlin 32 /*
306     * timer_tick():
307     */
308     static void timer_tick(struct timer *timer, void *extra)
309     {
310     struct vr41xx_data *d = (struct vr41xx_data *) extra;
311     d->pending_timer_interrupts ++;
312     }
313    
314    
315 dpavlin 30 DEVICE_TICK(vr41xx)
316 dpavlin 4 {
317     struct vr41xx_data *d = extra;
318    
319 dpavlin 32 if (d->pending_timer_interrupts > 0) {
320     if (d->cpumodel == 4121 || d->cpumodel == 4181)
321     cpu_interrupt(cpu, 3);
322     else
323     cpu_interrupt(cpu, 8 + VRIP_INTR_ETIMER);
324 dpavlin 4 }
325    
326     if (cpu->machine->use_x11)
327     vr41xx_keytick(cpu, d);
328     }
329    
330    
331     /*
332     * vr41xx_kiu():
333     *
334     * Keyboard Interface Unit. Return value is "odata".
335     * (See NetBSD's vrkiu.c for more info.)
336     */
337     static uint64_t vr41xx_kiu(struct cpu *cpu, int ofs, uint64_t idata,
338     int writeflag, struct vr41xx_data *d)
339     {
340     uint64_t odata = 0;
341    
342     switch (ofs) {
343     case KIUDAT0:
344     odata = d->d0; break;
345     case KIUDAT1:
346     odata = d->d1; break;
347     case KIUDAT2:
348     odata = d->d2; break;
349     case KIUDAT3:
350     odata = d->d3; break;
351     case KIUDAT4:
352     odata = d->d4; break;
353     case KIUDAT5:
354     odata = d->d5; break;
355     case KIUSCANREP:
356     if (writeflag == MEM_WRITE) {
357     debug("[ vr41xx KIU: setting KIUSCANREP to 0x%04x ]\n",
358     (int)idata);
359     /* TODO */
360     } else
361     fatal("[ vr41xx KIU: unimplemented read from "
362     "KIUSCANREP ]\n");
363     break;
364     case KIUSCANS:
365     if (writeflag == MEM_WRITE) {
366     debug("[ vr41xx KIU: write to KIUSCANS: 0x%04x: TODO"
367     " ]\n", (int)idata);
368     /* TODO */
369     } else
370     debug("[ vr41xx KIU: unimplemented read from "
371     "KIUSCANS ]\n");
372     break;
373     case KIUINT:
374     /* Interrupt. A wild guess: zero-on-write */
375     if (writeflag == MEM_WRITE) {
376     d->kiu_int_assert &= ~idata;
377     } else {
378     odata = d->kiu_int_assert;
379     }
380     recalc_kiu_int_assert(cpu, d);
381     break;
382     case KIURST:
383     /* Reset. */
384     break;
385     default:
386     if (writeflag == MEM_WRITE)
387     debug("[ vr41xx KIU: unimplemented write to offset "
388 dpavlin 24 "0x%x, data=0x%016"PRIx64" ]\n", ofs,
389     (uint64_t) idata);
390 dpavlin 4 else
391     debug("[ vr41xx KIU: unimplemented read from offset "
392     "0x%x ]\n", ofs);
393     }
394    
395     return odata;
396     }
397    
398    
399 dpavlin 22 DEVICE_ACCESS(vr41xx)
400 dpavlin 4 {
401     struct vr41xx_data *d = (struct vr41xx_data *) extra;
402     uint64_t idata = 0, odata = 0;
403     int regnr;
404     int revision = 0;
405    
406 dpavlin 18 if (writeflag == MEM_WRITE)
407     idata = memory_readmax64(cpu, data, len);
408    
409 dpavlin 4 regnr = relative_addr / sizeof(uint64_t);
410    
411     /* KIU ("Keyboard Interface Unit") is handled separately. */
412     if (relative_addr >= d->kiu_offset &&
413     relative_addr < d->kiu_offset + 0x20) {
414     odata = vr41xx_kiu(cpu, relative_addr - d->kiu_offset,
415     idata, writeflag, d);
416     goto ret;
417     }
418    
419     /* TODO: Maybe these should be handled separately as well? */
420    
421     switch (relative_addr) {
422 dpavlin 32
423 dpavlin 4 /* BCU: 0x00 .. 0x1c */
424     case BCUREVID_REG_W: /* 0x010 */
425     case BCU81REVID_REG_W: /* 0x014 */
426     /*
427     * TODO? Linux seems to read 0x14. The lowest bits are
428     * a divisor for PClock, bits 8 and up seem to be a
429     * divisor for VTClock (relative to PClock?)...
430     */
431     switch (d->cpumodel) {
432     case 4131: revision = BCUREVID_RID_4131; break;
433     case 4122: revision = BCUREVID_RID_4122; break;
434     case 4121: revision = BCUREVID_RID_4121; break;
435     case 4111: revision = BCUREVID_RID_4111; break;
436     case 4102: revision = BCUREVID_RID_4102; break;
437     case 4101: revision = BCUREVID_RID_4101; break;
438     case 4181: revision = BCUREVID_RID_4181; break;
439     }
440     odata = (revision << BCUREVID_RIDSHFT) | 0x020c;
441     break;
442     case BCU81CLKSPEED_REG_W: /* 0x018 */
443     /*
444     * TODO: Implement this for ALL cpu types:
445     */
446     odata = BCUCLKSPEED_DIVT4 << BCUCLKSPEED_DIVTSHFT;
447     break;
448    
449     /* DMAAU: 0x20 .. 0x3c */
450    
451     /* DCU: 0x40 .. 0x5c */
452    
453     /* CMU: 0x60 .. 0x7c */
454    
455     /* ICU: 0x80 .. 0xbc */
456     case 0x80: /* Level 1 system interrupt reg 1... */
457     if (writeflag == MEM_READ)
458     odata = d->sysint1;
459     else {
460     /* TODO: clear-on-write-one? */
461     d->sysint1 &= ~idata;
462     d->sysint1 &= 0xffff;
463     }
464     break;
465     case 0x88:
466     if (writeflag == MEM_READ)
467     odata = d->giuint;
468     else
469     d->giuint &= ~idata;
470     break;
471     case 0x8c:
472     if (writeflag == MEM_READ)
473     odata = d->msysint1;
474     else
475     d->msysint1 = idata;
476     break;
477     case 0x94:
478     if (writeflag == MEM_READ)
479     odata = d->giumask;
480     else
481     d->giumask = idata;
482     break;
483     case 0xa0: /* Level 1 system interrupt reg 2... */
484     if (writeflag == MEM_READ)
485     odata = d->sysint2;
486     else {
487     /* TODO: clear-on-write-one? */
488     d->sysint2 &= ~idata;
489     d->sysint2 &= 0xffff;
490     }
491     break;
492     case 0xa6:
493     if (writeflag == MEM_READ)
494     odata = d->msysint2;
495     else
496     d->msysint2 = idata;
497     break;
498    
499 dpavlin 32 /* RTC: */
500     case 0xc0:
501     case 0xc2:
502     case 0xc4:
503     {
504     struct timeval tv;
505     gettimeofday(&tv, NULL);
506     /* Adjust time by 120 years and 29 days. */
507     tv.tv_sec += (int64_t) (120*365 + 29) * 24*60*60;
508 dpavlin 4
509 dpavlin 32 switch (relative_addr) {
510     case 0xc0:
511     odata = (tv.tv_sec & 1) << 15;
512     break;
513     case 0xc2:
514     odata = (tv.tv_sec >> 1) & 0xffff;
515     break;
516     case 0xc4:
517     odata = (tv.tv_sec >> 17) & 0xffff;
518     break;
519     }
520     }
521     break;
522    
523     case 0xd0: /* RTCL1_L_REG_W */
524     if (writeflag == MEM_WRITE && idata != 0) {
525     int hz = RTCL1_L_HZ / idata;
526     debug("[ vr41xx: rtc interrupts at %i Hz ]\n", hz);
527     if (d->timer == NULL)
528     d->timer = timer_add(hz, timer_tick, d);
529     else
530     timer_update_frequency(d->timer, hz);
531     }
532     break;
533     case 0xd2: /* RTCL1_H_REG_W */
534     break;
535    
536 dpavlin 4 case 0x108:
537     if (writeflag == MEM_READ)
538     odata = d->giuint;
539     else
540     d->giuint &= ~idata;
541     break;
542     /* case 0x10a:
543     "High" part of GIU?
544     break;
545     */
546    
547     case 0x13e: /* on 4181? */
548     /* RTC interrupt register... */
549     /* Ack. timer interrupts? */
550     cpu_interrupt_ack(cpu, 8 + VRIP_INTR_ETIMER);
551 dpavlin 32 if (d->pending_timer_interrupts > 0)
552     d->pending_timer_interrupts --;
553 dpavlin 4 break;
554    
555     case 0x1de: /* on 4121? */
556     /* RTC interrupt register... */
557     /* Ack. timer interrupts? */
558     cpu_interrupt_ack(cpu, 3);
559 dpavlin 32 if (d->pending_timer_interrupts > 0)
560     d->pending_timer_interrupts --;
561 dpavlin 4 break;
562    
563     default:
564     if (writeflag == MEM_WRITE)
565     debug("[ vr41xx: unimplemented write to address "
566 dpavlin 24 "0x%"PRIx64", data=0x%016"PRIx64" ]\n",
567     (uint64_t) relative_addr, (uint64_t) idata);
568 dpavlin 4 else
569     debug("[ vr41xx: unimplemented read from address "
570 dpavlin 24 "0x%"PRIx64" ]\n", (uint64_t) relative_addr);
571 dpavlin 4 }
572    
573     ret:
574     /* Recalculate interrupt assertions: */
575     cpu_interrupt_ack(cpu, 8 + 31); /* TODO: hopefully nothing
576     useful at irq 15 in
577     sysint2 */
578    
579     if (writeflag == MEM_READ)
580     memory_writemax64(cpu, data, len, odata);
581    
582     return 1;
583     }
584    
585    
586     /*
587     * dev_vr41xx_init():
588     */
589     struct vr41xx_data *dev_vr41xx_init(struct machine *machine,
590     struct memory *mem, int cpumodel)
591     {
592     uint64_t baseaddr = 0;
593 dpavlin 12 char tmps[100];
594 dpavlin 4 struct vr41xx_data *d = malloc(sizeof(struct vr41xx_data));
595 dpavlin 12
596 dpavlin 4 if (d == NULL) {
597     fprintf(stderr, "out of memory\n");
598     exit(1);
599     }
600     memset(d, 0, sizeof(struct vr41xx_data));
601    
602     d->cpumodel = cpumodel;
603    
604     /* TODO: VRC4173 has the KIU at offset 0x100? */
605     d->kiu_offset = 0x180;
606 dpavlin 22 d->kiu_console_handle = console_start_slave_inputonly(
607     machine, "kiu", 1);
608 dpavlin 4 d->kiu_irq_nr = VRIP_INTR_KIU;
609    
610     switch (cpumodel) {
611     case 4101:
612     case 4102:
613     case 4111:
614     case 4121:
615     baseaddr = 0xb000000;
616     break;
617     case 4181:
618     baseaddr = 0xa000000;
619 dpavlin 18 dev_ram_init(machine, 0xb000000, 0x1000000, DEV_RAM_MIRROR,
620 dpavlin 4 0xa000000);
621     break;
622     case 4122:
623     case 4131:
624     baseaddr = 0xf000000;
625     break;
626     default:
627     printf("Unimplemented VR cpu model\n");
628     exit(1);
629     }
630    
631     memory_device_register(mem, "vr41xx", baseaddr, DEV_VR41XX_LENGTH,
632 dpavlin 20 dev_vr41xx_access, (void *)d, DM_DEFAULT, NULL);
633 dpavlin 4
634     /*
635     * TODO: Find out which controllers are at which addresses on
636     * which chips.
637     */
638     if (cpumodel == 4131) {
639 dpavlin 24 snprintf(tmps, sizeof(tmps), "ns16550 irq=%i addr=0x%"PRIx64" "
640     "name2=siu", 8+VRIP_INTR_SIU, (uint64_t) (baseaddr+0x800));
641 dpavlin 12 device_add(machine, tmps);
642 dpavlin 4 } else {
643     /* This is used by Linux and NetBSD: */
644 dpavlin 12 snprintf(tmps, sizeof(tmps), "ns16550 irq=%i addr=0x%x "
645     "name2=serial", 8+VRIP_INTR_SIU, 0xc000000);
646     device_add(machine, tmps);
647 dpavlin 4 }
648    
649     /* Hm... maybe this should not be here. TODO */
650     device_add(machine, "pcic addr=0x140003e0");
651    
652     machine_add_tickfunction(machine, dev_vr41xx_tick, d,
653 dpavlin 24 DEV_VR41XX_TICKSHIFT, 0.0);
654 dpavlin 4
655     /* Some machines (?) use ISA space at 0x15000000 instead of
656     0x14000000, eg IBM WorkPad Z50. */
657 dpavlin 18 dev_ram_init(machine, 0x15000000, 0x1000000, DEV_RAM_MIRROR,
658     0x14000000);
659 dpavlin 4
660     return d;
661     }
662    

  ViewVC Help
Powered by ViewVC 1.1.26