/[gxemul]/trunk/src/devices/dev_v3.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/devices/dev_v3.c

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Revision 42 - (hide annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 9542 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============
1 dpavlin 22 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 22 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 42 * $Id: dev_v3.c,v 1.9 2007/06/15 18:13:04 debug Exp $
29 dpavlin 22 *
30 dpavlin 42 * COMMENT: V3 Semiconductor PCI controller
31 dpavlin 22 *
32 dpavlin 34 * The ISA interrupt controller part forwards ISA interrupts as follows
33     * (on Algor P5064):
34     *
35     * ISA interrupt 3 and 4 -> MIPS interrupt 4 ("Local")
36     * All other ISA interrupts -> MIPS interrupt 2 ("ISA")
37     *
38 dpavlin 22 * See NetBSD's src/sys/arch/algor/pci/ for details.
39     */
40    
41     #include <stdio.h>
42     #include <stdlib.h>
43     #include <string.h>
44    
45     #include "bus_pci.h"
46     #include "cpu.h"
47     #include "device.h"
48     #include "devices.h"
49 dpavlin 34 #include "interrupt.h"
50 dpavlin 22 #include "machine.h"
51     #include "memory.h"
52     #include "misc.h"
53    
54    
55 dpavlin 34 struct v3_data {
56     struct interrupt irq_isa;
57     struct interrupt irq_local;
58     uint8_t secondary_mask1;
59    
60     struct pic8259_data* pic1;
61     struct pic8259_data* pic2;
62     int *ptr_to_pending_timer_interrupts;
63    
64     struct pci_data *pci_data;
65     uint16_t lb_map0;
66     };
67    
68    
69     /*
70     * v3_isa_interrupt_common():
71     */
72     void v3_isa_interrupt_common(struct v3_data *d, int old_isa_assert)
73     {
74     int new_isa_assert;
75    
76     /* Any interrupt assertions on PIC2 go to irq 2 on PIC1 */
77     /* (TODO: don't hardcode this here) */
78     if (d->pic2->irr & ~d->pic2->ier)
79     d->pic1->irr |= 0x04;
80     else
81     d->pic1->irr &= ~0x04;
82    
83     new_isa_assert = d->pic1->irr & ~d->pic1->ier;
84    
85     if (old_isa_assert == new_isa_assert)
86     return;
87    
88     if (new_isa_assert & d->secondary_mask1)
89     INTERRUPT_ASSERT(d->irq_local);
90     else
91     INTERRUPT_DEASSERT(d->irq_local);
92    
93     if (new_isa_assert & ~d->secondary_mask1)
94     INTERRUPT_ASSERT(d->irq_isa);
95     else
96     INTERRUPT_DEASSERT(d->irq_isa);
97     }
98    
99    
100     /*
101     * v3_isa_interrupt_assert():
102     *
103     * Called whenever an ISA device asserts an interrupt (0..15).
104     * If the interrupt number is 16, then it is a re-assert.
105     */
106     void v3_isa_interrupt_assert(struct interrupt *interrupt)
107     {
108     struct v3_data *d = interrupt->extra;
109     int old_isa_assert, line = interrupt->line;
110     int mask = 1 << (line & 7);
111    
112     old_isa_assert = d->pic1->irr & ~d->pic1->ier;
113    
114     if (line < 8)
115     d->pic1->irr |= mask;
116     else if (line < 16)
117     d->pic2->irr |= mask;
118    
119     v3_isa_interrupt_common(d, old_isa_assert);
120     }
121    
122    
123     /*
124     * v3_isa_interrupt_deassert():
125     *
126     * Called whenever an ISA device deasserts an interrupt (0..15).
127     * If the interrupt number is 16, then it is a re-assert.
128     */
129     void v3_isa_interrupt_deassert(struct interrupt *interrupt)
130     {
131     struct v3_data *d = interrupt->extra;
132     int line = interrupt->line, mask = 1 << (line & 7);
133     int old_irr1 = d->pic1->irr, old_isa_assert;
134    
135     old_isa_assert = old_irr1 & ~d->pic1->ier;
136    
137     if (line < 8)
138     d->pic1->irr &= ~mask;
139     else if (line < 16)
140     d->pic2->irr &= ~mask;
141    
142     /* If IRQ 0 has been cleared, then this is a timer interrupt.
143     Let's ack it here: */
144     if (old_irr1 & 1 && !(d->pic1->irr & 1) &&
145     d->ptr_to_pending_timer_interrupts != NULL &&
146     (*d->ptr_to_pending_timer_interrupts) > 0)
147     (*d->ptr_to_pending_timer_interrupts) --;
148    
149     v3_isa_interrupt_common(d, old_isa_assert);
150     }
151    
152    
153 dpavlin 22 DEVICE_ACCESS(v3_pci)
154     {
155     uint64_t idata = 0, odata = 0;
156     int bus, dev, func, reg;
157     struct v3_data *d = extra;
158    
159     if (writeflag == MEM_WRITE)
160     idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
161    
162     /* Decompose the tag: */
163     relative_addr &= 0xfffff;
164     relative_addr |= ((d->lb_map0 & 0xfff0) << 16);
165     bus = 0;
166     for (dev=24; dev<32; dev++)
167     if (relative_addr & (1 << dev))
168     break;
169     dev -= 24;
170     if (dev == 8) {
171     fatal("[ v3_pci: NO DEVICE? ]\n");
172     dev = 0;
173     }
174     func = (relative_addr >> 8) & 7;
175     reg = relative_addr & 0xfc;
176     bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
177    
178     /* Pass semi-direct PCI accesses onto bus_pci: */
179     bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
180     &odata : &idata, len, writeflag);
181    
182     if (writeflag == MEM_READ)
183     memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
184    
185     return 1;
186     }
187    
188    
189     DEVICE_ACCESS(v3)
190     {
191     struct v3_data *d = extra;
192     uint64_t idata = 0, odata = 0;
193    
194     if (writeflag == MEM_WRITE)
195     idata = memory_readmax64(cpu, data, len);
196    
197     switch (relative_addr) {
198    
199     case 0x06: /* PCI stat */
200     break;
201    
202     case 0x08: /* Revision */
203     odata = 4;
204     break;
205    
206     case 0x18: /* PCI DMA base 1 */
207     odata = 0x11000000;
208     break;
209    
210     case 0x5e: /* LB MAP0 */
211     if (writeflag == MEM_READ)
212     odata = d->lb_map0;
213     else
214     d->lb_map0 = idata;
215     break;
216    
217     case 0x62: /* PCI mem base 1 */
218     odata = 0x1100;
219     break;
220    
221     case 0x64: /* L2 BASE */
222     odata = 1; /* pci i/o enable */
223     break;
224    
225     case 0x66: /* Map 2 */
226     odata = 0x1d00;
227     break;
228    
229     default:if (writeflag == MEM_WRITE) {
230     fatal("[ v3: unimplemented write to "
231     "offset 0x%x: data=0x%x ]\n", (int)
232     relative_addr, (int)idata);
233     } else {
234     fatal("[ v3: unimplemented read from "
235     "offset 0x%x ]\n", (int)relative_addr);
236     }
237     }
238    
239     if (writeflag == MEM_READ)
240     memory_writemax64(cpu, data, len, odata);
241    
242     return 1;
243     }
244    
245    
246 dpavlin 34 DEVINIT(v3)
247 dpavlin 22 {
248     struct v3_data *d;
249 dpavlin 34 uint32_t isa_port_base = 0x1d000000;
250     char tmpstr[200];
251     char isa_irq_base[200];
252     char pci_irq_base[200];
253     int i;
254 dpavlin 22
255 dpavlin 42 CHECK_ALLOCATION(d = malloc(sizeof(struct v3_data)));
256 dpavlin 22 memset(d, 0, sizeof(struct v3_data));
257    
258 dpavlin 34 switch (devinit->machine->machine_type) {
259     case MACHINE_ALGOR:
260     snprintf(tmpstr, sizeof(tmpstr), "%s.4",
261     devinit->interrupt_path);
262     INTERRUPT_CONNECT(tmpstr, d->irq_local);
263    
264     snprintf(tmpstr, sizeof(tmpstr), "%s.2",
265     devinit->interrupt_path);
266     INTERRUPT_CONNECT(tmpstr, d->irq_isa);
267    
268     d->secondary_mask1 = 0x18;
269     break;
270    
271     default:fatal("!\n! WARNING: v3 for non-implemented machine"
272     " type %i\n!\n", devinit->machine->machine_type);
273     exit(1);
274     }
275    
276     /*
277     * Register the 16 possible ISA interrupts, plus a dummy. The
278     * dummy is used by re-asserts.
279     */
280     for (i=0; i<17; i++) {
281     struct interrupt template;
282     char n[300];
283     snprintf(n, sizeof(n), "%s.v3.isa.%i",
284     devinit->interrupt_path, i);
285     memset(&template, 0, sizeof(template));
286     template.line = i;
287     template.name = n;
288     template.extra = d;
289     template.interrupt_assert = v3_isa_interrupt_assert;
290     template.interrupt_deassert = v3_isa_interrupt_deassert;
291     interrupt_handler_register(&template);
292     }
293    
294     /* Register two 8259 PICs: */
295     snprintf(tmpstr, sizeof(tmpstr), "8259 irq=%s.v3.isa.16 addr=0x%llx",
296     devinit->interrupt_path, (long long)(isa_port_base + 0x20));
297     d->pic1 = devinit->machine->isa_pic_data.pic1 =
298     device_add(devinit->machine, tmpstr);
299     d->ptr_to_pending_timer_interrupts =
300     devinit->machine->isa_pic_data.pending_timer_interrupts;
301    
302     snprintf(tmpstr, sizeof(tmpstr), "8259 irq=%s.v3.isa.2 addr=0x%llx",
303     devinit->interrupt_path, (long long)(isa_port_base + 0xa0));
304     d->pic2 = devinit->machine->isa_pic_data.pic2 =
305     device_add(devinit->machine, tmpstr);
306    
307     snprintf(isa_irq_base, sizeof(isa_irq_base), "%s.v3",
308     devinit->interrupt_path);
309     snprintf(pci_irq_base, sizeof(pci_irq_base), "%s.v3",
310     devinit->interrupt_path);
311    
312 dpavlin 22 /* Register a PCI bus: */
313     d->pci_data = bus_pci_init(
314 dpavlin 34 devinit->machine,
315     pci_irq_base /* pciirq: TODO */,
316     0x1d000000, /* pci device io offset */
317     0x11000000, /* pci device mem offset: TODO */
318     0x00000000, /* PCI portbase: TODO */
319     0x00000000, /* PCI membase: TODO */
320     pci_irq_base, /* PCI irqbase */
321     isa_port_base, /* ISA portbase */
322     0x10000000, /* ISA membase */
323     isa_irq_base); /* ISA irqbase */
324 dpavlin 22
325 dpavlin 34 switch (devinit->machine->machine_type) {
326 dpavlin 22 case MACHINE_ALGOR:
327 dpavlin 34 bus_pci_add(devinit->machine, d->pci_data,
328     devinit->machine->memory, 0, 2, 0, "piix3_isa");
329     bus_pci_add(devinit->machine, d->pci_data,
330     devinit->machine->memory, 0, 2, 1, "piix3_ide");
331 dpavlin 22 break;
332     default:fatal("!\n! WARNING: v3 for non-implemented machine"
333 dpavlin 34 " type %i\n!\n", devinit->machine->machine_type);
334 dpavlin 22 exit(1);
335     }
336    
337     /* PCI configuration space: */
338 dpavlin 34 memory_device_register(devinit->machine->memory, "v3_pci",
339     0x1ee00000, 0x100000, dev_v3_pci_access, d, DM_DEFAULT, NULL);
340 dpavlin 22
341     /* PCI controller: */
342 dpavlin 34 memory_device_register(devinit->machine->memory, "v3",
343     0x1ef00000, 0x1000, dev_v3_access, d, DM_DEFAULT, NULL);
344 dpavlin 22
345 dpavlin 34 devinit->return_ptr = d->pci_data;
346    
347     return 1;
348 dpavlin 22 }
349    
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