/[gxemul]/trunk/src/devices/dev_v3.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 9586 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 dpavlin 22 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 22 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: dev_v3.c,v 1.8 2007/01/20 13:26:20 debug Exp $
29 dpavlin 22 *
30     * V3 Semiconductor PCI controller.
31     *
32 dpavlin 34 * The ISA interrupt controller part forwards ISA interrupts as follows
33     * (on Algor P5064):
34     *
35     * ISA interrupt 3 and 4 -> MIPS interrupt 4 ("Local")
36     * All other ISA interrupts -> MIPS interrupt 2 ("ISA")
37     *
38 dpavlin 22 * See NetBSD's src/sys/arch/algor/pci/ for details.
39     */
40    
41     #include <stdio.h>
42     #include <stdlib.h>
43     #include <string.h>
44    
45     #include "bus_pci.h"
46     #include "cpu.h"
47     #include "device.h"
48     #include "devices.h"
49 dpavlin 34 #include "interrupt.h"
50 dpavlin 22 #include "machine.h"
51     #include "memory.h"
52     #include "misc.h"
53    
54    
55 dpavlin 34 struct v3_data {
56     struct interrupt irq_isa;
57     struct interrupt irq_local;
58     uint8_t secondary_mask1;
59    
60     struct pic8259_data* pic1;
61     struct pic8259_data* pic2;
62     int *ptr_to_pending_timer_interrupts;
63    
64     struct pci_data *pci_data;
65     uint16_t lb_map0;
66     };
67    
68    
69     /*
70     * v3_isa_interrupt_common():
71     */
72     void v3_isa_interrupt_common(struct v3_data *d, int old_isa_assert)
73     {
74     int new_isa_assert;
75    
76     /* Any interrupt assertions on PIC2 go to irq 2 on PIC1 */
77     /* (TODO: don't hardcode this here) */
78     if (d->pic2->irr & ~d->pic2->ier)
79     d->pic1->irr |= 0x04;
80     else
81     d->pic1->irr &= ~0x04;
82    
83     new_isa_assert = d->pic1->irr & ~d->pic1->ier;
84    
85     if (old_isa_assert == new_isa_assert)
86     return;
87    
88     if (new_isa_assert & d->secondary_mask1)
89     INTERRUPT_ASSERT(d->irq_local);
90     else
91     INTERRUPT_DEASSERT(d->irq_local);
92    
93     if (new_isa_assert & ~d->secondary_mask1)
94     INTERRUPT_ASSERT(d->irq_isa);
95     else
96     INTERRUPT_DEASSERT(d->irq_isa);
97     }
98    
99    
100     /*
101     * v3_isa_interrupt_assert():
102     *
103     * Called whenever an ISA device asserts an interrupt (0..15).
104     * If the interrupt number is 16, then it is a re-assert.
105     */
106     void v3_isa_interrupt_assert(struct interrupt *interrupt)
107     {
108     struct v3_data *d = interrupt->extra;
109     int old_isa_assert, line = interrupt->line;
110     int mask = 1 << (line & 7);
111    
112     old_isa_assert = d->pic1->irr & ~d->pic1->ier;
113    
114     if (line < 8)
115     d->pic1->irr |= mask;
116     else if (line < 16)
117     d->pic2->irr |= mask;
118    
119     v3_isa_interrupt_common(d, old_isa_assert);
120     }
121    
122    
123     /*
124     * v3_isa_interrupt_deassert():
125     *
126     * Called whenever an ISA device deasserts an interrupt (0..15).
127     * If the interrupt number is 16, then it is a re-assert.
128     */
129     void v3_isa_interrupt_deassert(struct interrupt *interrupt)
130     {
131     struct v3_data *d = interrupt->extra;
132     int line = interrupt->line, mask = 1 << (line & 7);
133     int old_irr1 = d->pic1->irr, old_isa_assert;
134    
135     old_isa_assert = old_irr1 & ~d->pic1->ier;
136    
137     if (line < 8)
138     d->pic1->irr &= ~mask;
139     else if (line < 16)
140     d->pic2->irr &= ~mask;
141    
142     /* If IRQ 0 has been cleared, then this is a timer interrupt.
143     Let's ack it here: */
144     if (old_irr1 & 1 && !(d->pic1->irr & 1) &&
145     d->ptr_to_pending_timer_interrupts != NULL &&
146     (*d->ptr_to_pending_timer_interrupts) > 0)
147     (*d->ptr_to_pending_timer_interrupts) --;
148    
149     v3_isa_interrupt_common(d, old_isa_assert);
150     }
151    
152    
153 dpavlin 22 DEVICE_ACCESS(v3_pci)
154     {
155     uint64_t idata = 0, odata = 0;
156     int bus, dev, func, reg;
157     struct v3_data *d = extra;
158    
159     if (writeflag == MEM_WRITE)
160     idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
161    
162     /* Decompose the tag: */
163     relative_addr &= 0xfffff;
164     relative_addr |= ((d->lb_map0 & 0xfff0) << 16);
165     bus = 0;
166     for (dev=24; dev<32; dev++)
167     if (relative_addr & (1 << dev))
168     break;
169     dev -= 24;
170     if (dev == 8) {
171     fatal("[ v3_pci: NO DEVICE? ]\n");
172     dev = 0;
173     }
174     func = (relative_addr >> 8) & 7;
175     reg = relative_addr & 0xfc;
176     bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
177    
178     /* Pass semi-direct PCI accesses onto bus_pci: */
179     bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
180     &odata : &idata, len, writeflag);
181    
182     if (writeflag == MEM_READ)
183     memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
184    
185     return 1;
186     }
187    
188    
189     DEVICE_ACCESS(v3)
190     {
191     struct v3_data *d = extra;
192     uint64_t idata = 0, odata = 0;
193    
194     if (writeflag == MEM_WRITE)
195     idata = memory_readmax64(cpu, data, len);
196    
197     switch (relative_addr) {
198    
199     case 0x06: /* PCI stat */
200     break;
201    
202     case 0x08: /* Revision */
203     odata = 4;
204     break;
205    
206     case 0x18: /* PCI DMA base 1 */
207     odata = 0x11000000;
208     break;
209    
210     case 0x5e: /* LB MAP0 */
211     if (writeflag == MEM_READ)
212     odata = d->lb_map0;
213     else
214     d->lb_map0 = idata;
215     break;
216    
217     case 0x62: /* PCI mem base 1 */
218     odata = 0x1100;
219     break;
220    
221     case 0x64: /* L2 BASE */
222     odata = 1; /* pci i/o enable */
223     break;
224    
225     case 0x66: /* Map 2 */
226     odata = 0x1d00;
227     break;
228    
229     default:if (writeflag == MEM_WRITE) {
230     fatal("[ v3: unimplemented write to "
231     "offset 0x%x: data=0x%x ]\n", (int)
232     relative_addr, (int)idata);
233     } else {
234     fatal("[ v3: unimplemented read from "
235     "offset 0x%x ]\n", (int)relative_addr);
236     }
237     }
238    
239     if (writeflag == MEM_READ)
240     memory_writemax64(cpu, data, len, odata);
241    
242     return 1;
243     }
244    
245    
246 dpavlin 34 DEVINIT(v3)
247 dpavlin 22 {
248     struct v3_data *d;
249 dpavlin 34 uint32_t isa_port_base = 0x1d000000;
250     char tmpstr[200];
251     char isa_irq_base[200];
252     char pci_irq_base[200];
253     int i;
254 dpavlin 22
255     d = malloc(sizeof(struct v3_data));
256     if (d == NULL) {
257     fprintf(stderr, "out of memory\n");
258     exit(1);
259     }
260     memset(d, 0, sizeof(struct v3_data));
261    
262 dpavlin 34 switch (devinit->machine->machine_type) {
263     case MACHINE_ALGOR:
264     snprintf(tmpstr, sizeof(tmpstr), "%s.4",
265     devinit->interrupt_path);
266     INTERRUPT_CONNECT(tmpstr, d->irq_local);
267    
268     snprintf(tmpstr, sizeof(tmpstr), "%s.2",
269     devinit->interrupt_path);
270     INTERRUPT_CONNECT(tmpstr, d->irq_isa);
271    
272     d->secondary_mask1 = 0x18;
273     break;
274    
275     default:fatal("!\n! WARNING: v3 for non-implemented machine"
276     " type %i\n!\n", devinit->machine->machine_type);
277     exit(1);
278     }
279    
280     /*
281     * Register the 16 possible ISA interrupts, plus a dummy. The
282     * dummy is used by re-asserts.
283     */
284     for (i=0; i<17; i++) {
285     struct interrupt template;
286     char n[300];
287     snprintf(n, sizeof(n), "%s.v3.isa.%i",
288     devinit->interrupt_path, i);
289     memset(&template, 0, sizeof(template));
290     template.line = i;
291     template.name = n;
292     template.extra = d;
293     template.interrupt_assert = v3_isa_interrupt_assert;
294     template.interrupt_deassert = v3_isa_interrupt_deassert;
295     interrupt_handler_register(&template);
296     }
297    
298     /* Register two 8259 PICs: */
299     snprintf(tmpstr, sizeof(tmpstr), "8259 irq=%s.v3.isa.16 addr=0x%llx",
300     devinit->interrupt_path, (long long)(isa_port_base + 0x20));
301     d->pic1 = devinit->machine->isa_pic_data.pic1 =
302     device_add(devinit->machine, tmpstr);
303     d->ptr_to_pending_timer_interrupts =
304     devinit->machine->isa_pic_data.pending_timer_interrupts;
305    
306     snprintf(tmpstr, sizeof(tmpstr), "8259 irq=%s.v3.isa.2 addr=0x%llx",
307     devinit->interrupt_path, (long long)(isa_port_base + 0xa0));
308     d->pic2 = devinit->machine->isa_pic_data.pic2 =
309     device_add(devinit->machine, tmpstr);
310    
311     snprintf(isa_irq_base, sizeof(isa_irq_base), "%s.v3",
312     devinit->interrupt_path);
313     snprintf(pci_irq_base, sizeof(pci_irq_base), "%s.v3",
314     devinit->interrupt_path);
315    
316 dpavlin 22 /* Register a PCI bus: */
317     d->pci_data = bus_pci_init(
318 dpavlin 34 devinit->machine,
319     pci_irq_base /* pciirq: TODO */,
320     0x1d000000, /* pci device io offset */
321     0x11000000, /* pci device mem offset: TODO */
322     0x00000000, /* PCI portbase: TODO */
323     0x00000000, /* PCI membase: TODO */
324     pci_irq_base, /* PCI irqbase */
325     isa_port_base, /* ISA portbase */
326     0x10000000, /* ISA membase */
327     isa_irq_base); /* ISA irqbase */
328 dpavlin 22
329 dpavlin 34 switch (devinit->machine->machine_type) {
330 dpavlin 22 case MACHINE_ALGOR:
331 dpavlin 34 bus_pci_add(devinit->machine, d->pci_data,
332     devinit->machine->memory, 0, 2, 0, "piix3_isa");
333     bus_pci_add(devinit->machine, d->pci_data,
334     devinit->machine->memory, 0, 2, 1, "piix3_ide");
335 dpavlin 22 break;
336     default:fatal("!\n! WARNING: v3 for non-implemented machine"
337 dpavlin 34 " type %i\n!\n", devinit->machine->machine_type);
338 dpavlin 22 exit(1);
339     }
340    
341     /* PCI configuration space: */
342 dpavlin 34 memory_device_register(devinit->machine->memory, "v3_pci",
343     0x1ee00000, 0x100000, dev_v3_pci_access, d, DM_DEFAULT, NULL);
344 dpavlin 22
345     /* PCI controller: */
346 dpavlin 34 memory_device_register(devinit->machine->memory, "v3",
347     0x1ef00000, 0x1000, dev_v3_access, d, DM_DEFAULT, NULL);
348 dpavlin 22
349 dpavlin 34 devinit->return_ptr = d->pci_data;
350    
351     return 1;
352 dpavlin 22 }
353    
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