/[gxemul]/trunk/src/devices/dev_unreadable.c
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revision 4 by dpavlin, Mon Oct 8 16:18:00 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2004-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2004-2006  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *     *  
27   *   *
28   *  $Id: dev_unreadable.c,v 1.9 2005/02/25 06:14:30 debug Exp $   *  $Id: dev_unreadable.c,v 1.12 2006/02/09 20:02:59 debug Exp $
29   *     *  
30   *  A simple device which returns an error for all accesses (both reads and   *  A simple device which returns an error for all accesses (both reads and
31   *  writes).   *  writes).
# Line 44  Line 44 
44  /*  /*
45   *  dev_unreadable_access():   *  dev_unreadable_access():
46   */   */
47  int dev_unreadable_access(struct cpu *cpu, struct memory *mem,  DEVICE_ACCESS(unreadable)
         uint64_t relative_addr, unsigned char *data, size_t len,  
         int writeflag, void *extra)  
48  {  {
49          return 0;          return 0;
50  }  }
51    
52    
53  /*  DEVINIT(unreadable)
  *  devinit_unreadable():  
  */  
 int devinit_unreadable(struct devinit *devinit)  
54  {  {
55          memory_device_register(devinit->machine->memory,          memory_device_register(devinit->machine->memory,
56              devinit->name, devinit->addr, devinit->len,              devinit->name, devinit->addr, devinit->len,
57              dev_unreadable_access, NULL, MEM_DEFAULT, NULL);              dev_unreadable_access, NULL, DM_DEFAULT, NULL);
58    
59          return 1;          return 1;
60  }  }
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