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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_ssc.c,v 1.23 2005/10/26 14:37:04 debug Exp $ |
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* |
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* Serial controller on DECsystem 5400 and 5800. |
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* Known as System Support Chip on VAX 3600 (KA650). |
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* |
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* Described around page 80 in the kn210tm1.pdf. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "console.h" |
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#include "cpu.h" |
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#include "devices.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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|
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#define RX_INT_ENABLE 0x40 |
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#define RX_AVAIL 0x80 |
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#define TX_INT_ENABLE 0x40 |
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#define TX_READY 0x80 |
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|
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|
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/* |
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* _TXRX is for debugging putchar/getchar. The other |
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* one is more general. |
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*/ |
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/* #define SSC_DEBUG_TXRX */ |
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#define SSC_DEBUG |
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|
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struct ssc_data { |
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int irq_nr; |
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int console_handle; |
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int use_fb; |
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|
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int rx_ctl; |
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int tx_ctl; |
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|
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uint32_t *csrp; |
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}; |
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|
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|
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/* |
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* dev_ssc_tick(): |
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*/ |
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void dev_ssc_tick(struct cpu *cpu, void *extra) |
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{ |
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struct ssc_data *d = extra; |
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|
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d->tx_ctl |= TX_READY; /* transmitter always ready */ |
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|
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d->rx_ctl &= ~RX_AVAIL; |
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if (console_charavail(d->console_handle)) |
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d->rx_ctl |= RX_AVAIL; |
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|
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/* rx interrupts enabled, and char avail? */ |
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if (d->rx_ctl & RX_INT_ENABLE && d->rx_ctl & RX_AVAIL) { |
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/* TODO: This is for 5800 only! */ |
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|
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if (d->csrp != NULL) { |
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unsigned char txvector = 0xf8; |
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(*d->csrp) |= 0x10000000; |
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cpu->memory_rw(cpu, cpu->mem, 0x40000050, &txvector, |
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1, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL); |
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cpu_interrupt(cpu, 2); |
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} |
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} |
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|
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/* tx interrupts enabled? */ |
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if (d->tx_ctl & TX_INT_ENABLE) { |
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/* TODO: This is for 5800 only! */ |
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|
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if (d->csrp != NULL) { |
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unsigned char txvector = 0xfc; |
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(*d->csrp) |= 0x10000000; |
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cpu->memory_rw(cpu, cpu->mem, 0x40000050, &txvector, |
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1, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL); |
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cpu_interrupt(cpu, 2); |
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} |
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} |
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} |
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|
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|
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/* |
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* dev_ssc_access(): |
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*/ |
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int dev_ssc_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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uint64_t idata = 0, odata = 0; |
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struct ssc_data *d = extra; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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dev_ssc_tick(cpu, extra); |
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|
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switch (relative_addr) { |
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case 0x0080: /* receive status */ |
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if (writeflag==MEM_READ) { |
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odata = d->rx_ctl; |
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#ifdef SSC_DEBUG_TXRX |
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debug("[ ssc: read from 0x%08lx: 0x%02x ]\n", |
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(long)relative_addr, (int)odata); |
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#endif |
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} else { |
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d->rx_ctl = idata; |
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|
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/* TODO: This only works for 5800 */ |
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if (d->csrp != NULL) { |
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(*d->csrp) &= ~0x10000000; |
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cpu_interrupt_ack(cpu, 2); |
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} |
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#ifdef SSC_DEBUG_TXRX |
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debug("[ ssc: write to 0x%08lx: 0x%02x ]\n", |
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(long)relative_addr, (int)idata); |
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#endif |
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} |
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|
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break; |
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case 0x0084: /* receive data */ |
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if (writeflag==MEM_READ) { |
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#ifdef SSC_DEBUG_TXRX |
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debug("[ ssc: read from 0x%08lx ]\n", |
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(long)relative_addr); |
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#endif |
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if (console_charavail(d->console_handle)) |
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odata = console_readchar(d->console_handle); |
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} else { |
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#ifdef SSC_DEBUG_TXRX |
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debug("[ ssc: write to 0x%08lx: 0x%02x ]\n", |
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(long)relative_addr, (int)idata); |
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#endif |
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} |
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|
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break; |
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case 0x0088: /* transmit status */ |
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if (writeflag==MEM_READ) { |
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odata = d->tx_ctl; |
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#ifdef SSC_DEBUG_TXRX |
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debug("[ ssc: read from 0x%08lx: 0x%04x ]\n", |
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(long)relative_addr, (int)odata); |
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#endif |
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} else { |
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d->tx_ctl = idata; |
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|
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/* TODO: This only works for 5800 */ |
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if (d->csrp != NULL) { |
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(*d->csrp) &= ~0x10000000; |
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cpu_interrupt_ack(cpu, 2); |
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} |
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#ifdef SSC_DEBUG_TXRX |
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debug("[ ssc: write to 0x%08lx: 0x%02x ]\n", |
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(long)relative_addr, (int)idata); |
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#endif |
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} |
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|
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break; |
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case 0x008c: /* transmit data */ |
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if (writeflag==MEM_READ) { |
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debug("[ ssc: read from 0x%08lx ]\n", |
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(long)relative_addr); |
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} else { |
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/* debug("[ ssc: write to 0x%08lx: 0x%02x ]\n", |
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(long)relative_addr, (int)idata); */ |
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console_putchar(d->console_handle, idata); |
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} |
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|
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break; |
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case 0x0100: |
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if (writeflag==MEM_READ) { |
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odata = 128; |
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#ifdef SSC_DEBUG_TXRX |
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debug("[ ssc: read from 0x%08lx: 0x%08lx ]\n", |
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(long)relative_addr, (long)odata); |
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#endif |
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} else { |
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#ifdef SSC_DEBUG_TXRX |
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debug("[ ssc: write to 0x%08lx: 0x%08x ]\n", |
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(long)relative_addr, idata); |
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#endif |
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} |
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|
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break; |
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case 0x0108: |
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if (writeflag==MEM_READ) { |
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debug("[ ssc: read from 0x%08lx ]\n", |
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(long)relative_addr); |
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} else { |
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#ifdef SSC_DEBUG |
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debug("[ ssc: write to 0x%08lx: 0x%08x ]\n", |
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(long)relative_addr, (int)idata); |
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#endif |
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} |
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|
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break; |
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default: |
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if (writeflag==MEM_READ) { |
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debug("[ ssc: read from 0x%08lx ]\n", |
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(long)relative_addr); |
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} else { |
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debug("[ ssc: write to 0x%08lx: 0x%08x ]\n", |
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(long)relative_addr, (int)idata); |
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} |
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} |
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|
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dev_ssc_tick(cpu, extra); |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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/* |
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* dev_ssc_init(): |
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*/ |
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void dev_ssc_init(struct machine *machine, struct memory *mem, |
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uint64_t baseaddr, int irq_nr, int use_fb, uint32_t *csrp) |
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{ |
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struct ssc_data *d; |
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|
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d = malloc(sizeof(struct ssc_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct ssc_data)); |
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d->irq_nr = irq_nr; |
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d->use_fb = use_fb; |
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d->csrp = csrp; |
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d->console_handle = console_start_slave(machine, "SSC"); |
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|
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memory_device_register(mem, "ssc", baseaddr, DEV_SSC_LENGTH, |
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dev_ssc_access, d, MEM_DEFAULT, NULL); |
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|
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machine_add_tickfunction(machine, dev_ssc_tick, d, 14); |
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} |
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