/[gxemul]/trunk/src/devices/dev_sii.c
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Contents of /trunk/src/devices/dev_sii.c

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 12968 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 /*
2 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_sii.c,v 1.19 2007/01/05 15:20:06 debug Exp $
29 *
30 * SII SCSI controller, used in some DECstation systems.
31 *
32 * TODO: This is huge and ugly. Fix this.
33 */
34
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38
39 #include "cpu.h"
40 #include "devices.h"
41 #include "interrupt.h"
42 #include "machine.h"
43 #include "memory.h"
44 #include "misc.h"
45
46 #include "siireg.h"
47
48
49 #define SII_TICK_SHIFT 14
50
51
52 struct sii_data {
53 struct interrupt irq;
54
55 uint64_t buf_start;
56 uint64_t buf_end;
57
58 int connected;
59 int connected_to_id;
60
61 int register_choice;
62 SIIRegs siiregs;
63 uint16_t *regs;
64 };
65
66
67 /*
68 * combine_sii_bits():
69 *
70 * Combines some bits of CSTAT and DSTAT that are connected.
71 */
72 void combine_sii_bits(struct sii_data *d)
73 {
74 int ci, di;
75
76 di = ((d->siiregs.dstat & SII_MIS) |
77 (d->siiregs.dstat & SII_IBF) |
78 (d->siiregs.dstat & SII_TBE) |
79 (d->siiregs.dstat & SII_DNE))==0? 0 : SII_DI;
80
81 ci = ((d->siiregs.cstat & SII_RST) |
82 (d->siiregs.cstat & SII_BER) |
83 (d->siiregs.cstat & SII_OBC) |
84 (d->siiregs.cstat & SII_BUF) |
85 (d->siiregs.cstat & SII_LDN) |
86 (d->siiregs.cstat & SII_SCH))==0? 0 : SII_CI;
87
88 d->siiregs.cstat &= ~(SII_CI | SII_DI);
89 d->siiregs.dstat &= ~(SII_CI | SII_DI);
90
91 d->siiregs.cstat |= (ci | di);
92 d->siiregs.dstat |= (ci | di);
93 }
94
95
96 /*
97 * dev_sii_tick():
98 */
99 void dev_sii_tick(struct cpu *cpu, void *extra)
100 {
101 struct sii_data *d = extra;
102
103 /* ? */
104 d->siiregs.dstat = (d->siiregs.dstat & ~0x7)
105 | ((d->siiregs.dstat + 1) & 0x7);
106
107 /* SCSI Commands: */
108
109 if (d->siiregs.comm & SII_CHRESET) { /* (I,T,D) */
110 /* debug("[ sii: command TODO: CHRESET ]\n"); */
111 }
112
113 if (d->siiregs.comm & SII_DISCON) { /* (I,T,D) */
114 /* debug("[ sii: command TODO: DISCON ]\n"); */
115 d->siiregs.cstat &= ~SII_CON; /* Connected */
116
117 if (d->connected) {
118 d->siiregs.cstat |= SII_SCH; /* State change */
119 d->connected = 0;
120 }
121
122 d->siiregs.cstat &= ~SII_SIP; /* Selection in progress */
123 d->siiregs.comm &= ~SII_DISCON;
124 }
125
126 if (d->siiregs.comm & SII_REQDATA) { /* (T) */
127 /* debug("[ sii: command TODO: REQDATA ]\n"); */
128 }
129
130 if (d->siiregs.comm & SII_SELECT) { /* (D) */
131 /* debug("[ sii: command SELECT ]\n"); */
132 d->siiregs.comm &= ~SII_SELECT;
133
134 /* slcsr contains the other target's id */
135 d->siiregs.cstat |= SII_SIP; /* Selection in progress */
136 d->connected = 0;
137 d->connected_to_id = 0;
138
139 /* Is the target available for selection?
140 TODO: make this nicer */
141 #if 0
142 if ((d->siiregs.slcsr & 7) == 0) {
143 d->siiregs.cstat |= SII_CON; /* Connected */
144 d->siiregs.cstat |= SII_SCH; /* State change */
145 d->siiregs.cstat &= ~SII_SIP; /* Sel. in progress */
146
147 d->connected = 1;
148 d->connected_to_id = 0;
149 }
150 #endif
151 }
152
153 if (d->siiregs.comm & SII_INXFER
154 && (d->siiregs.comm & 0x70) == (d->siiregs.cstat & 0x70) &&
155 (d->siiregs.comm & 0x03) == (d->siiregs.dstat & 0x03) &&
156 !(d->siiregs.cstat & SII_SIP)) { /* (I,T) */
157 debug("[ sii: command INXFER to scsiid=%i ]\n",
158 d->siiregs.slcsr);
159 if (d->siiregs.comm & SII_DMA)
160 debug("[ sii DMA: TODO ]\n");
161 else {
162 debug("[ sii: transmitting byte 0x%02x using "
163 "PIO mode ]\n", d->siiregs.data);
164 d->siiregs.comm &= ~SII_INXFER;
165
166 /* d->siiregs.dstat |= SII_DNE; */
167 /* Done, only for DMA? */
168 d->siiregs.dstat |= SII_TBE; /* Buffer empty? */
169 }
170 }
171
172 combine_sii_bits(d);
173
174 if (d->siiregs.csr & SII_IE && d->siiregs.cstat & (SII_CI | SII_DI))
175 INTERRUPT_ASSERT(d->irq);
176 else
177 INTERRUPT_DEASSERT(d->irq);
178 }
179
180
181 DEVICE_ACCESS(sii)
182 {
183 uint64_t idata = 0, odata = 0;
184 int regnr;
185 struct sii_data *d = extra;
186
187 if (relative_addr & 3) {
188 debug("[ sii relative_addr = 0x%x !!! ]\n",
189 (int) relative_addr);
190 return 0;
191 }
192
193 dev_sii_tick(cpu, extra);
194
195 if (writeflag == MEM_WRITE)
196 idata = memory_readmax64(cpu, data, len);
197
198 regnr = relative_addr / 2;
199 odata = d->regs[regnr];
200
201 switch (relative_addr) {
202 case 0x00: /* SII_SDB: Diagnostic */
203 if (writeflag == MEM_READ) {
204 debug("[ sii: read from SDB (data=0x%04x) ]\n",
205 d->regs[regnr]);
206 } else {
207 debug("[ sii: write to SDB (data=0x%04x) ]\n",
208 (int)idata);
209 d->regs[regnr] = idata;
210 return 1;
211 }
212 break;
213 case 0x0c: /* SII_CSR: Control/status */
214 if (writeflag == MEM_READ) {
215 debug("[ sii: read from CSR (data=0x%04x) ]\n",
216 d->regs[regnr]);
217 } else {
218 debug("[ sii: write to CSR (data=0x%04x: %s %s "
219 "%s %s %s) ]\n", (int)idata,
220 idata & SII_HPM? "HPM" : "!hpm",
221 idata & SII_RSE? "RSE" : "!rse",
222 idata & SII_SLE? "SLE" : "!sle",
223 idata & SII_PCE? "PCE" : "!pce",
224 idata & SII_IE? "IE" : "!ie");
225 d->regs[regnr] = idata;
226 return 1;
227 }
228 break;
229 case 0x10: /* SII_ID: SCSI ID */
230 if (writeflag == MEM_READ) {
231 debug("[ sii: read from ID (data=0x%04x) ]\n",
232 d->regs[regnr]);
233 } else {
234 debug("[ sii: write to ID (data=0x%04x: scsi id %i)"
235 " ]\n", (int)idata, (int)(idata & 7));
236 if (!(idata & SII_ID_IO))
237 debug("WARNING: sii ID bit SII_ID_IO not "
238 "set on write!\n");
239 idata &= ~SII_ID_IO;
240 if ((idata & ~0x7) != 0)
241 debug("WARNING: sii ID bits that should "
242 "be zero are not zero!\n");
243 idata &= 0x7;
244 d->regs[regnr] = idata & 0x7;
245 return 1;
246 }
247 break;
248 case 0x14: /* SII_SLCSR: Selector control */
249 if (writeflag == MEM_READ) {
250 debug("[ sii: read from SLCSR (data=0x%04x: "
251 "scsi_id=%i) ]\n", d->regs[regnr],
252 d->regs[regnr] & 7);
253 } else {
254 debug("[ sii: write to SLCSR (data=0x%04x: "
255 "scsi_id=%i) ]\n", (int)idata, (int)(idata & 7));
256 if ((idata & ~0x7) != 0)
257 debug("WARNING: sii SLCSR bits that should "
258 "be zero are not zero!\n");
259 idata &= 0x7;
260 d->regs[regnr] = idata & 0x7;
261 return 1;
262 }
263 break;
264 case 0x18: /* SII_DESTAT: Selection detector status */
265 if (writeflag == MEM_READ) {
266 /* TODO: set DESTAT from somewhere else? */
267 debug("[ sii: read from DESTAT (data=0x%04x: "
268 "scsi_id=%i) ]\n", d->regs[regnr],
269 d->regs[regnr] & 7);
270 } else {
271 debug("[ sii: write to DESTAT (data=0x%04x: "
272 "scsi_id=%i) ]\n", (int)idata, (int)(idata & 7));
273 debug("WARNING: sii DESTAT is read-only!\n");
274 return 1;
275 }
276 break;
277 case 0x20: /* SII_DATA: Data register */
278 if (writeflag == MEM_READ) {
279 /* TODO */
280 debug("[ sii: read from DATA (data=0x%04x) ]\n",
281 d->regs[regnr]);
282 } else {
283 /* TODO */
284 debug("[ sii: write to DATA (data=0x%04x) ]\n",
285 (int)idata);
286 idata &= 0xff;
287 d->regs[regnr] = idata;
288 return 1;
289 }
290 break;
291 case 0x24: /* SII_DMCTRL: DMA control */
292 if (writeflag == MEM_READ) {
293 debug("[ sii: read from DMCTRL (data=0x%04x) ]\n",
294 d->regs[regnr]);
295 } else {
296 debug("[ sii: write to DMCTRL (data=0x%04x: %s) ]\n",
297 (int)idata, (idata & 3)==0? "async" : "sync");
298 if ((idata & ~0x3) != 0)
299 debug("WARNING: sii DMCTRL bits that "
300 "should be zero are not zero!\n");
301 idata &= 0x3;
302 d->regs[regnr] = idata;
303 return 1;
304 }
305 break;
306 case 0x48: /* SII_CSTAT: Connection status */
307 if (writeflag == MEM_READ) {
308 debug("[ sii: read from CSTAT (data=0x%04x) ]\n",
309 d->regs[regnr]);
310 } else {
311 debug("[ sii: write to CSTAT (data=0x%04x) ]\n",
312 (int)idata);
313
314 /* readonly / writeoncetoclear bits according
315 to page 21 in the DS3100 manual: */
316 if (idata & (1<<13)) {
317 idata &= ~(1<<13); d->regs[regnr] &= ~(1<<13);
318 }
319 if (idata & (1<<12)) {
320 idata &= ~(1<<12); d->regs[regnr] &= ~(1<<12);
321 }
322 if (idata & (1<<11)) {
323 /* is this actually write-1-to-clear? */
324 idata &= ~(1<<11); d->regs[regnr] &= ~(1<<11);
325 }
326 if (idata & (1<<9)) {
327 /* ? */
328 idata &= ~(1<<9); d->regs[regnr] &= ~(1<<9);
329 }
330 if (idata & (1<<8)) {
331 /* ? */
332 idata &= ~(1<<8); d->regs[regnr] &= ~(1<<8);
333 }
334 if (idata & (1<<7)) {
335 idata &= ~(1<<7); d->regs[regnr] &= ~(1<<7);
336 }
337 if (idata & (1<<3)) {
338 idata &= ~(1<<3); d->regs[regnr] &= ~(1<<3);
339 }
340
341 /* Read-only bits are taken from the old register: */
342 idata &= ~0x3bf7;
343 idata |= d->regs[regnr] & 0x3bf7;
344
345 d->regs[regnr] = idata;
346 return 1;
347 }
348 break;
349 case 0x4c: /* SII_DSTAT: Data transfer status */
350 if (writeflag == MEM_READ) {
351 debug("[ sii: read from DSTAT (data=0x%04x) ]\n",
352 d->regs[regnr]);
353 } else {
354 debug("[ sii: write to DSTAT (data=0x%04x) ]\n",
355 (int)idata);
356
357 /* readonly / writeoncetoclear bits
358 according to page 22 in the DS3100 manual: */
359 if (idata & (1<<13)) {
360 idata &= ~(1<<13); d->regs[regnr] &= ~(1<<13);
361 }
362 if (idata & (1<<11)) {
363 /* is this write-1-to-clear? */
364 idata &= ~(1<<11); d->regs[regnr] &= ~(1<<11);
365 }
366 if (idata & (1<<10)) {
367 /* is this write-1-to-clear? */
368 idata &= ~(1<<10); d->regs[regnr] &= ~(1<<10);
369 }
370 if (idata & (1<<4)) {
371 /* is this write-1-to-clear? */
372 idata &= ~(1<<4); d->regs[regnr] &= ~(1<<4);
373 }
374 if (idata & (1<<3)) {
375 idata &= ~(1<<3); d->regs[regnr] &= ~(1<<3);
376 }
377
378 /* Read-only bits are taken from the old register: */
379 idata &= ~0x0c17;
380 idata |= d->regs[regnr] & 0x0c17;
381
382 d->regs[regnr] = idata;
383 return 1;
384 }
385 break;
386 case 0x50: /* SII_COMM: Command */
387 if (writeflag == MEM_READ) {
388 debug("[ sii: read from COMM (data=0x%04x) ]\n",
389 d->regs[regnr]);
390 } else {
391 debug("[ sii: write to COMM (data=0x%04x: %s %s "
392 "%s command=0x%02x rest=0x%02x) ]\n", (int)idata,
393 idata & SII_DMA? "DMA" : "!dma",
394 idata & SII_DO_RST? "RST" : "!rst",
395 idata & SII_RSL? "RSL" : "!rsl",
396 /* command, 5 bits: */
397 (int)((idata >> 7) & 0x1f),
398 /* rest, 7 bits: */
399 (int)(idata & 0x3f));
400
401 if (idata & SII_DO_RST) {
402 /* Reset: TODO */
403 }
404
405 idata &= ~SII_DO_RST;
406 d->regs[regnr] = idata;
407
408 dev_sii_tick(cpu, extra);
409 return 1;
410 }
411 break;
412 case 0x54: /* SII_DICTRL: Diagnostics control */
413 if (writeflag == MEM_READ) {
414 debug("[ sii: read from DICTRL (data=0x%04x) ]\n",
415 d->regs[regnr]);
416 } else {
417 debug("[ sii: write to DICTRL (data=0x%04x: "
418 "port=%s) ]\n", (int)idata,
419 idata & SII_PRE? "enabled" : "disabled");
420 if ((idata & ~0xf) != 0)
421 debug("WARNING: sii DICTRL bits that "
422 "should be zero are not zero!\n");
423 d->regs[regnr] = idata;
424 return 1;
425 }
426 break;
427 default:
428 if (writeflag==MEM_READ) {
429 debug("[ sii: read from %08lx (data=0x%04x) ]\n",
430 (long)relative_addr, d->regs[regnr]);
431 } else {
432 debug("[ sii: write to %08lx (data=0x%04x) ]\n",
433 (long)relative_addr, (int)idata);
434 d->regs[regnr] = idata;
435 }
436 }
437
438 if (writeflag == MEM_READ)
439 memory_writemax64(cpu, data, len, odata);
440
441 return 1;
442 }
443
444
445 /*
446 * dev_sii_init():
447 */
448 void dev_sii_init(struct machine *machine, struct memory *mem,
449 uint64_t baseaddr, uint64_t buf_start, uint64_t buf_end,
450 char *irq_path)
451 {
452 struct sii_data *d = malloc(sizeof(struct sii_data));
453 if (d == NULL) {
454 fprintf(stderr, "out of memory\n");
455 exit(1);
456 }
457
458 memset(d, 0, sizeof(struct sii_data));
459 INTERRUPT_CONNECT(irq_path, d->irq);
460 d->buf_start = buf_start;
461 d->buf_end = buf_end;
462 d->regs = (uint16_t *) &d->siiregs;
463
464 memory_device_register(mem, "sii", baseaddr, DEV_SII_LENGTH,
465 dev_sii_access, (void *)d, DM_DEFAULT, NULL);
466
467 machine_add_tickfunction(machine, dev_sii_tick, d,
468 SII_TICK_SHIFT, 0.0);
469 }
470

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