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dpavlin |
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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: dev_sii.c,v 1.15 2005/11/13 00:14:10 debug Exp $ |
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dpavlin |
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* |
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* SII SCSI controller, used in some DECstation systems. |
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* |
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* TODO: This is huge and ugly. Fix this. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "cpu.h" |
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#include "devices.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "siireg.h" |
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#define SII_TICK_SHIFT 14 |
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struct sii_data { |
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int irq_nr; |
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uint64_t buf_start; |
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uint64_t buf_end; |
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int connected; |
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int connected_to_id; |
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int register_choice; |
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SIIRegs siiregs; |
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uint16_t *regs; |
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}; |
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/* |
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* combine_sii_bits(): |
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* |
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* Combines some bits of CSTAT and DSTAT that are connected. |
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*/ |
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void combine_sii_bits(struct sii_data *d) |
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{ |
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int ci, di; |
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di = ((d->siiregs.dstat & SII_MIS) | |
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(d->siiregs.dstat & SII_IBF) | |
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(d->siiregs.dstat & SII_TBE) | |
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(d->siiregs.dstat & SII_DNE))==0? 0 : SII_DI; |
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ci = ((d->siiregs.cstat & SII_RST) | |
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(d->siiregs.cstat & SII_BER) | |
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(d->siiregs.cstat & SII_OBC) | |
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(d->siiregs.cstat & SII_BUF) | |
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(d->siiregs.cstat & SII_LDN) | |
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(d->siiregs.cstat & SII_SCH))==0? 0 : SII_CI; |
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d->siiregs.cstat &= ~(SII_CI | SII_DI); |
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d->siiregs.dstat &= ~(SII_CI | SII_DI); |
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d->siiregs.cstat |= (ci | di); |
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d->siiregs.dstat |= (ci | di); |
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} |
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/* |
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* dev_sii_tick(): |
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*/ |
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void dev_sii_tick(struct cpu *cpu, void *extra) |
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{ |
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struct sii_data *d = extra; |
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/* ? */ |
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d->siiregs.dstat = (d->siiregs.dstat & ~0x7) |
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| ((d->siiregs.dstat + 1) & 0x7); |
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/* SCSI Commands: */ |
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if (d->siiregs.comm & SII_CHRESET) { /* (I,T,D) */ |
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/* debug("[ sii: command TODO: CHRESET ]\n"); */ |
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} |
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if (d->siiregs.comm & SII_DISCON) { /* (I,T,D) */ |
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/* debug("[ sii: command TODO: DISCON ]\n"); */ |
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d->siiregs.cstat &= ~SII_CON; /* Connected */ |
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if (d->connected) { |
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d->siiregs.cstat |= SII_SCH; /* State change */ |
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d->connected = 0; |
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} |
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d->siiregs.cstat &= ~SII_SIP; /* Selection in progress */ |
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d->siiregs.comm &= ~SII_DISCON; |
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} |
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if (d->siiregs.comm & SII_REQDATA) { /* (T) */ |
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/* debug("[ sii: command TODO: REQDATA ]\n"); */ |
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} |
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if (d->siiregs.comm & SII_SELECT) { /* (D) */ |
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/* debug("[ sii: command SELECT ]\n"); */ |
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d->siiregs.comm &= ~SII_SELECT; |
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/* slcsr contains the other target's id */ |
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d->siiregs.cstat |= SII_SIP; /* Selection in progress */ |
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d->connected = 0; |
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d->connected_to_id = 0; |
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/* Is the target available for selection? |
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TODO: make this nicer */ |
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#if 0 |
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if ((d->siiregs.slcsr & 7) == 0) { |
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d->siiregs.cstat |= SII_CON; /* Connected */ |
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d->siiregs.cstat |= SII_SCH; /* State change */ |
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d->siiregs.cstat &= ~SII_SIP; /* Sel. in progress */ |
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d->connected = 1; |
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d->connected_to_id = 0; |
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} |
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#endif |
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} |
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if (d->siiregs.comm & SII_INXFER |
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&& (d->siiregs.comm & 0x70) == (d->siiregs.cstat & 0x70) && |
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(d->siiregs.comm & 0x03) == (d->siiregs.dstat & 0x03) && |
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!(d->siiregs.cstat & SII_SIP)) { /* (I,T) */ |
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debug("[ sii: command INXFER to scsiid=%i ]\n", |
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d->siiregs.slcsr); |
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if (d->siiregs.comm & SII_DMA) |
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debug("[ sii DMA: TODO ]\n"); |
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else { |
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debug("[ sii: transmitting byte 0x%02x using " |
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"PIO mode ]\n", d->siiregs.data); |
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d->siiregs.comm &= ~SII_INXFER; |
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/* d->siiregs.dstat |= SII_DNE; */ |
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/* Done, only for DMA? */ |
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d->siiregs.dstat |= SII_TBE; /* Buffer empty? */ |
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} |
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} |
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combine_sii_bits(d); |
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if (d->siiregs.csr & SII_IE && d->siiregs.cstat & (SII_CI | SII_DI)) |
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cpu_interrupt(cpu, d->irq_nr); |
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else |
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cpu_interrupt_ack(cpu, d->irq_nr); |
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} |
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/* |
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* dev_sii_access(): |
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*/ |
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int dev_sii_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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uint64_t idata = 0, odata = 0; |
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int regnr; |
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struct sii_data *d = extra; |
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if (relative_addr & 3) { |
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debug("[ sii relative_addr = 0x%x !!! ]\n", |
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(int) relative_addr); |
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return 0; |
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} |
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dev_sii_tick(cpu, extra); |
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dpavlin |
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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dpavlin |
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regnr = relative_addr / 2; |
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odata = d->regs[regnr]; |
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switch (relative_addr) { |
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case 0x00: /* SII_SDB: Diagnostic */ |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from SDB (data=0x%04x) ]\n", |
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d->regs[regnr]); |
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} else { |
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debug("[ sii: write to SDB (data=0x%04x) ]\n", |
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(int)idata); |
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d->regs[regnr] = idata; |
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return 1; |
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} |
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break; |
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case 0x0c: /* SII_CSR: Control/status */ |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from CSR (data=0x%04x) ]\n", |
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d->regs[regnr]); |
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} else { |
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debug("[ sii: write to CSR (data=0x%04x: %s %s " |
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"%s %s %s) ]\n", (int)idata, |
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idata & SII_HPM? "HPM" : "!hpm", |
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idata & SII_RSE? "RSE" : "!rse", |
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idata & SII_SLE? "SLE" : "!sle", |
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idata & SII_PCE? "PCE" : "!pce", |
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idata & SII_IE? "IE" : "!ie"); |
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d->regs[regnr] = idata; |
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return 1; |
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} |
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break; |
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case 0x10: /* SII_ID: SCSI ID */ |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from ID (data=0x%04x) ]\n", |
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d->regs[regnr]); |
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} else { |
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debug("[ sii: write to ID (data=0x%04x: scsi id %i)" |
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" ]\n", (int)idata, (int)(idata & 7)); |
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if (!(idata & SII_ID_IO)) |
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debug("WARNING: sii ID bit SII_ID_IO not " |
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"set on write!\n"); |
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idata &= ~SII_ID_IO; |
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if ((idata & ~0x7) != 0) |
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debug("WARNING: sii ID bits that should " |
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"be zero are not zero!\n"); |
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idata &= 0x7; |
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d->regs[regnr] = idata & 0x7; |
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return 1; |
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} |
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break; |
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case 0x14: /* SII_SLCSR: Selector control */ |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from SLCSR (data=0x%04x: " |
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"scsi_id=%i) ]\n", d->regs[regnr], |
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d->regs[regnr] & 7); |
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} else { |
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debug("[ sii: write to SLCSR (data=0x%04x: " |
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"scsi_id=%i) ]\n", (int)idata, (int)(idata & 7)); |
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if ((idata & ~0x7) != 0) |
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debug("WARNING: sii SLCSR bits that should " |
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"be zero are not zero!\n"); |
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idata &= 0x7; |
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d->regs[regnr] = idata & 0x7; |
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return 1; |
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} |
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break; |
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case 0x18: /* SII_DESTAT: Selection detector status */ |
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if (writeflag == MEM_READ) { |
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/* TODO: set DESTAT from somewhere else? */ |
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debug("[ sii: read from DESTAT (data=0x%04x: " |
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"scsi_id=%i) ]\n", d->regs[regnr], |
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d->regs[regnr] & 7); |
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} else { |
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debug("[ sii: write to DESTAT (data=0x%04x: " |
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"scsi_id=%i) ]\n", (int)idata, (int)(idata & 7)); |
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debug("WARNING: sii DESTAT is read-only!\n"); |
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return 1; |
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} |
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break; |
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case 0x20: /* SII_DATA: Data register */ |
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if (writeflag == MEM_READ) { |
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/* TODO */ |
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debug("[ sii: read from DATA (data=0x%04x) ]\n", |
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d->regs[regnr]); |
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} else { |
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/* TODO */ |
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debug("[ sii: write to DATA (data=0x%04x) ]\n", |
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(int)idata); |
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idata &= 0xff; |
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d->regs[regnr] = idata; |
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return 1; |
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} |
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break; |
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case 0x24: /* SII_DMCTRL: DMA control */ |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from DMCTRL (data=0x%04x) ]\n", |
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d->regs[regnr]); |
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} else { |
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debug("[ sii: write to DMCTRL (data=0x%04x: %s) ]\n", |
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(int)idata, (idata & 3)==0? "async" : "sync"); |
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if ((idata & ~0x3) != 0) |
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debug("WARNING: sii DMCTRL bits that " |
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"should be zero are not zero!\n"); |
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idata &= 0x3; |
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d->regs[regnr] = idata; |
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return 1; |
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} |
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break; |
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case 0x48: /* SII_CSTAT: Connection status */ |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from CSTAT (data=0x%04x) ]\n", |
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d->regs[regnr]); |
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} else { |
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debug("[ sii: write to CSTAT (data=0x%04x) ]\n", |
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(int)idata); |
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317 |
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/* readonly / writeoncetoclear bits according |
318 |
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to page 21 in the DS3100 manual: */ |
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if (idata & (1<<13)) { |
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idata &= ~(1<<13); d->regs[regnr] &= ~(1<<13); |
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} |
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if (idata & (1<<12)) { |
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idata &= ~(1<<12); d->regs[regnr] &= ~(1<<12); |
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} |
325 |
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if (idata & (1<<11)) { |
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/* is this actually write-1-to-clear? */ |
327 |
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idata &= ~(1<<11); d->regs[regnr] &= ~(1<<11); |
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} |
329 |
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if (idata & (1<<9)) { |
330 |
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/* ? */ |
331 |
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idata &= ~(1<<9); d->regs[regnr] &= ~(1<<9); |
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} |
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if (idata & (1<<8)) { |
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/* ? */ |
335 |
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idata &= ~(1<<8); d->regs[regnr] &= ~(1<<8); |
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} |
337 |
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if (idata & (1<<7)) { |
338 |
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idata &= ~(1<<7); d->regs[regnr] &= ~(1<<7); |
339 |
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} |
340 |
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if (idata & (1<<3)) { |
341 |
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idata &= ~(1<<3); d->regs[regnr] &= ~(1<<3); |
342 |
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} |
343 |
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344 |
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/* Read-only bits are taken from the old register: */ |
345 |
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idata &= ~0x3bf7; |
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idata |= d->regs[regnr] & 0x3bf7; |
347 |
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348 |
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d->regs[regnr] = idata; |
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return 1; |
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} |
351 |
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break; |
352 |
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case 0x4c: /* SII_DSTAT: Data transfer status */ |
353 |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from DSTAT (data=0x%04x) ]\n", |
355 |
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d->regs[regnr]); |
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} else { |
357 |
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debug("[ sii: write to DSTAT (data=0x%04x) ]\n", |
358 |
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(int)idata); |
359 |
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360 |
|
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/* readonly / writeoncetoclear bits |
361 |
|
|
according to page 22 in the DS3100 manual: */ |
362 |
|
|
if (idata & (1<<13)) { |
363 |
|
|
idata &= ~(1<<13); d->regs[regnr] &= ~(1<<13); |
364 |
|
|
} |
365 |
|
|
if (idata & (1<<11)) { |
366 |
|
|
/* is this write-1-to-clear? */ |
367 |
|
|
idata &= ~(1<<11); d->regs[regnr] &= ~(1<<11); |
368 |
|
|
} |
369 |
|
|
if (idata & (1<<10)) { |
370 |
|
|
/* is this write-1-to-clear? */ |
371 |
|
|
idata &= ~(1<<10); d->regs[regnr] &= ~(1<<10); |
372 |
|
|
} |
373 |
|
|
if (idata & (1<<4)) { |
374 |
|
|
/* is this write-1-to-clear? */ |
375 |
|
|
idata &= ~(1<<4); d->regs[regnr] &= ~(1<<4); |
376 |
|
|
} |
377 |
|
|
if (idata & (1<<3)) { |
378 |
|
|
idata &= ~(1<<3); d->regs[regnr] &= ~(1<<3); |
379 |
|
|
} |
380 |
|
|
|
381 |
|
|
/* Read-only bits are taken from the old register: */ |
382 |
|
|
idata &= ~0x0c17; |
383 |
|
|
idata |= d->regs[regnr] & 0x0c17; |
384 |
|
|
|
385 |
|
|
d->regs[regnr] = idata; |
386 |
|
|
return 1; |
387 |
|
|
} |
388 |
|
|
break; |
389 |
|
|
case 0x50: /* SII_COMM: Command */ |
390 |
|
|
if (writeflag == MEM_READ) { |
391 |
|
|
debug("[ sii: read from COMM (data=0x%04x) ]\n", |
392 |
|
|
d->regs[regnr]); |
393 |
|
|
} else { |
394 |
|
|
debug("[ sii: write to COMM (data=0x%04x: %s %s " |
395 |
|
|
"%s command=0x%02x rest=0x%02x) ]\n", (int)idata, |
396 |
|
|
idata & SII_DMA? "DMA" : "!dma", |
397 |
|
|
idata & SII_DO_RST? "RST" : "!rst", |
398 |
|
|
idata & SII_RSL? "RSL" : "!rsl", |
399 |
|
|
/* command, 5 bits: */ |
400 |
|
|
(int)((idata >> 7) & 0x1f), |
401 |
|
|
/* rest, 7 bits: */ |
402 |
|
|
(int)(idata & 0x3f)); |
403 |
|
|
|
404 |
|
|
if (idata & SII_DO_RST) { |
405 |
|
|
/* Reset: TODO */ |
406 |
|
|
} |
407 |
|
|
|
408 |
|
|
idata &= ~SII_DO_RST; |
409 |
|
|
d->regs[regnr] = idata; |
410 |
|
|
|
411 |
|
|
dev_sii_tick(cpu, extra); |
412 |
|
|
return 1; |
413 |
|
|
} |
414 |
|
|
break; |
415 |
|
|
case 0x54: /* SII_DICTRL: Diagnostics control */ |
416 |
|
|
if (writeflag == MEM_READ) { |
417 |
|
|
debug("[ sii: read from DICTRL (data=0x%04x) ]\n", |
418 |
|
|
d->regs[regnr]); |
419 |
|
|
} else { |
420 |
|
|
debug("[ sii: write to DICTRL (data=0x%04x: " |
421 |
|
|
"port=%s) ]\n", (int)idata, |
422 |
|
|
idata & SII_PRE? "enabled" : "disabled"); |
423 |
|
|
if ((idata & ~0xf) != 0) |
424 |
|
|
debug("WARNING: sii DICTRL bits that " |
425 |
|
|
"should be zero are not zero!\n"); |
426 |
|
|
d->regs[regnr] = idata; |
427 |
|
|
return 1; |
428 |
|
|
} |
429 |
|
|
break; |
430 |
|
|
default: |
431 |
|
|
if (writeflag==MEM_READ) { |
432 |
|
|
debug("[ sii: read from %08lx (data=0x%04x) ]\n", |
433 |
|
|
(long)relative_addr, d->regs[regnr]); |
434 |
|
|
} else { |
435 |
|
|
debug("[ sii: write to %08lx (data=0x%04x) ]\n", |
436 |
|
|
(long)relative_addr, (int)idata); |
437 |
|
|
d->regs[regnr] = idata; |
438 |
|
|
} |
439 |
|
|
} |
440 |
|
|
|
441 |
|
|
if (writeflag == MEM_READ) |
442 |
|
|
memory_writemax64(cpu, data, len, odata); |
443 |
|
|
|
444 |
|
|
return 1; |
445 |
|
|
} |
446 |
|
|
|
447 |
|
|
|
448 |
|
|
/* |
449 |
|
|
* dev_sii_init(): |
450 |
|
|
*/ |
451 |
|
|
void dev_sii_init(struct machine *machine, struct memory *mem, |
452 |
|
|
uint64_t baseaddr, uint64_t buf_start, uint64_t buf_end, int irq_nr) |
453 |
|
|
{ |
454 |
|
|
struct sii_data *d = malloc(sizeof(struct sii_data)); |
455 |
|
|
if (d == NULL) { |
456 |
|
|
fprintf(stderr, "out of memory\n"); |
457 |
|
|
exit(1); |
458 |
|
|
} |
459 |
|
|
|
460 |
|
|
memset(d, 0, sizeof(struct sii_data)); |
461 |
|
|
d->irq_nr = irq_nr; |
462 |
|
|
d->buf_start = buf_start; |
463 |
|
|
d->buf_end = buf_end; |
464 |
|
|
|
465 |
|
|
d->regs = (uint16_t *) &d->siiregs; |
466 |
|
|
|
467 |
|
|
memory_device_register(mem, "sii", baseaddr, DEV_SII_LENGTH, |
468 |
dpavlin |
20 |
dev_sii_access, (void *)d, DM_DEFAULT, NULL); |
469 |
dpavlin |
4 |
|
470 |
|
|
machine_add_tickfunction(machine, dev_sii_tick, d, SII_TICK_SHIFT); |
471 |
|
|
} |
472 |
|
|
|