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/* |
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* Copyright (C) 2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_sh4.c,v 1.21 2006/11/02 05:43:44 debug Exp $ |
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* |
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* SH4 processor specific memory mapped registers (0xf0000000 - 0xffffffff). |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "console.h" |
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#include "cpu.h" |
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#include "device.h" |
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#include "devices.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "timer.h" |
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|
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#include "sh4_bscreg.h" |
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#include "sh4_cache.h" |
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#include "sh4_exception.h" |
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#include "sh4_intcreg.h" |
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#include "sh4_mmu.h" |
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#include "sh4_scifreg.h" |
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#include "sh4_tmureg.h" |
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|
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|
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#define SH4_REG_BASE 0xff000000 |
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#define SH4_TICK_SHIFT 14 |
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#define N_SH4_TIMERS 3 |
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|
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/* #define debug fatal */ |
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|
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struct sh4_data { |
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int scif_console_handle; |
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|
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/* Bus State Controller: */ |
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uint32_t unknown_2c; |
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uint32_t unknown_30; |
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|
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/* Timer Management Unit: */ |
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struct timer *sh4_timer; |
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uint32_t tocr; |
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uint32_t tstr; |
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uint32_t tcnt[N_SH4_TIMERS]; |
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uint32_t tcor[N_SH4_TIMERS]; |
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uint32_t tcr[N_SH4_TIMERS]; |
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int timer_interrupts_pending[N_SH4_TIMERS]; |
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double timer_hz[N_SH4_TIMERS]; |
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}; |
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|
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|
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#define SH4_PSEUDO_TIMER_HZ 100.0 |
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|
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|
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/* |
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* sh4_timer_tick(): |
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* |
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* This function is called SH4_PSEUDO_TIMER_HZ times per real-world second. |
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* Its job is to update the SH4 timer counters, and if necessary, increase |
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* the number of pending interrupts. |
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*/ |
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static void sh4_timer_tick(struct timer *t, void *extra) |
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{ |
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struct sh4_data *d = (struct sh4_data *) extra; |
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int i; |
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|
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for (i=0; i<N_SH4_TIMERS; i++) { |
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int32_t old = d->tcnt[i]; |
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|
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/* printf("tcnt[%i] = %08x tcor[%i] = %08x\n", |
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i, d->tcnt[i], i, d->tcor[i]); */ |
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|
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/* Only update timers that are currently started: */ |
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if (!(d->tstr & (TSTR_STR0 << i))) |
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continue; |
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|
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/* Update the current count: */ |
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d->tcnt[i] -= d->timer_hz[i] / SH4_PSEUDO_TIMER_HZ; |
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|
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/* Has the timer underflowed? */ |
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if ((int32_t)d->tcnt[i] < 0 && old >= 0) { |
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d->tcr[i] |= TCR_UNF; |
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|
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if (d->tcr[i] & TCR_UNIE) |
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d->timer_interrupts_pending[i] ++; |
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|
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/* |
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* Set tcnt[i] to tcor[i]. Note: Since this function |
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* is only called now and then, adding tcor[i] to |
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* tcnt[i] produces more correct values for long |
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* running timers. |
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*/ |
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d->tcnt[i] += d->tcor[i]; |
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|
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/* At least make sure that tcnt is non-negative... */ |
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if ((int32_t)d->tcnt[i] < 0) |
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d->tcnt[i] = 0; |
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} |
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} |
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} |
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|
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|
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DEVICE_TICK(sh4) |
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{ |
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struct sh4_data *d = (struct sh4_data *) extra; |
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int i; |
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|
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for (i=0; i<N_SH4_TIMERS; i++) |
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if (d->timer_interrupts_pending[i] > 0) { |
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cpu_interrupt(cpu, SH_INTEVT_TMU0_TUNI0 + 0x20 * i); |
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d->tcr[i] |= TCR_UNF; |
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} |
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} |
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|
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|
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DEVICE_ACCESS(sh4_itlb_aa) |
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{ |
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uint64_t idata = 0, odata = 0; |
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int e = (relative_addr & SH4_ITLB_E_MASK) >> SH4_ITLB_E_SHIFT; |
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|
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if (writeflag == MEM_WRITE) { |
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int safe_to_invalidate = 0; |
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uint32_t old_hi = cpu->cd.sh.itlb_hi[e]; |
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if ((cpu->cd.sh.itlb_lo[e] & SH4_PTEL_SZ_MASK)==SH4_PTEL_SZ_4K) |
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safe_to_invalidate = 1; |
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|
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idata = memory_readmax64(cpu, data, len); |
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cpu->cd.sh.itlb_hi[e] &= |
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~(SH4_PTEH_VPN_MASK | SH4_PTEH_ASID_MASK); |
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cpu->cd.sh.itlb_hi[e] |= (idata & |
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(SH4_ITLB_AA_VPN_MASK | SH4_ITLB_AA_ASID_MASK)); |
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cpu->cd.sh.itlb_lo[e] &= ~SH4_PTEL_V; |
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if (idata & SH4_ITLB_AA_V) |
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cpu->cd.sh.itlb_lo[e] |= SH4_PTEL_V; |
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|
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if (safe_to_invalidate) |
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cpu->invalidate_translation_caches(cpu, |
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old_hi & ~0xfff, INVALIDATE_VADDR); |
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else |
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cpu->invalidate_translation_caches(cpu, |
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0, INVALIDATE_ALL); |
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} else { |
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odata = cpu->cd.sh.itlb_hi[e] & |
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(SH4_ITLB_AA_VPN_MASK | SH4_ITLB_AA_ASID_MASK); |
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if (cpu->cd.sh.itlb_lo[e] & SH4_PTEL_V) |
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odata |= SH4_ITLB_AA_V; |
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memory_writemax64(cpu, data, len, odata); |
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} |
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|
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return 1; |
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} |
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|
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|
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DEVICE_ACCESS(sh4_itlb_da1) |
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{ |
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uint32_t mask = SH4_PTEL_SH | SH4_PTEL_C | SH4_PTEL_SZ_MASK | |
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SH4_PTEL_PR_MASK | SH4_PTEL_V | 0x1ffffc00; |
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uint64_t idata = 0, odata = 0; |
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int e = (relative_addr & SH4_ITLB_E_MASK) >> SH4_ITLB_E_SHIFT; |
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|
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if (relative_addr & 0x800000) { |
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fatal("sh4_itlb_da1: TODO: da2 area\n"); |
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exit(1); |
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} |
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|
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if (writeflag == MEM_WRITE) { |
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int safe_to_invalidate = 0; |
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if ((cpu->cd.sh.itlb_lo[e] & SH4_PTEL_SZ_MASK)==SH4_PTEL_SZ_4K) |
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safe_to_invalidate = 1; |
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|
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idata = memory_readmax64(cpu, data, len); |
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cpu->cd.sh.itlb_lo[e] &= ~mask; |
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cpu->cd.sh.itlb_lo[e] |= (idata & mask); |
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|
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if (safe_to_invalidate) |
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cpu->invalidate_translation_caches(cpu, |
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cpu->cd.sh.itlb_hi[e] & ~0xfff, INVALIDATE_VADDR); |
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else |
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cpu->invalidate_translation_caches(cpu, |
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0, INVALIDATE_ALL); |
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} else { |
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odata = cpu->cd.sh.itlb_lo[e] & mask; |
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memory_writemax64(cpu, data, len, odata); |
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} |
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|
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return 1; |
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} |
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|
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|
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DEVICE_ACCESS(sh4_utlb_aa) |
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{ |
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uint64_t idata = 0, odata = 0; |
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int i, e = (relative_addr & SH4_UTLB_E_MASK) >> SH4_UTLB_E_SHIFT; |
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int a = relative_addr & SH4_UTLB_A; |
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|
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if (writeflag == MEM_WRITE) { |
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int n_hits = 0; |
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int safe_to_invalidate = 0; |
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uint32_t vaddr_to_invalidate = 0; |
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|
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idata = memory_readmax64(cpu, data, len); |
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if (a) { |
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for (i=-SH_N_ITLB_ENTRIES; i<SH_N_UTLB_ENTRIES; i++) { |
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uint32_t lo, hi; |
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uint32_t mask = 0xfffff000; |
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int sh; |
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|
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if (i < 0) { |
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lo = cpu->cd.sh.itlb_lo[ |
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i + SH_N_ITLB_ENTRIES]; |
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hi = cpu->cd.sh.itlb_hi[ |
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i + SH_N_ITLB_ENTRIES]; |
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} else { |
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lo = cpu->cd.sh.utlb_lo[i]; |
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hi = cpu->cd.sh.utlb_hi[i]; |
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} |
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|
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sh = lo & SH4_PTEL_SH; |
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if (!(lo & SH4_PTEL_V)) |
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continue; |
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|
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switch (lo & SH4_PTEL_SZ_MASK) { |
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case SH4_PTEL_SZ_1K: mask = 0xfffffc00; break; |
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case SH4_PTEL_SZ_64K: mask = 0xffff0000; break; |
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case SH4_PTEL_SZ_1M: mask = 0xfff00000; break; |
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} |
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|
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if ((hi & mask) != (idata & mask)) |
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continue; |
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|
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if ((lo & SH4_PTEL_SZ_MASK) == |
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SH4_PTEL_SZ_4K) { |
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safe_to_invalidate = 1; |
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vaddr_to_invalidate = hi & mask; |
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} |
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|
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if (!sh && (hi & SH4_PTEH_ASID_MASK) != |
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(cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) |
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continue; |
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|
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if (i < 0) { |
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cpu->cd.sh.itlb_lo[i] &= ~SH4_PTEL_V; |
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if (idata & SH4_UTLB_AA_V) |
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cpu->cd.sh.itlb_lo[i] |= |
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SH4_PTEL_V; |
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} else { |
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cpu->cd.sh.utlb_lo[i] &= |
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~(SH4_PTEL_D | SH4_PTEL_V); |
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if (idata & SH4_UTLB_AA_D) |
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cpu->cd.sh.utlb_lo[i] |= |
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SH4_PTEL_D; |
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if (idata & SH4_UTLB_AA_V) |
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cpu->cd.sh.utlb_lo[i] |= |
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SH4_PTEL_V; |
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} |
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|
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if (i >= 0) |
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n_hits ++; |
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} |
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|
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if (n_hits > 1) |
290 |
sh_exception(cpu, |
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EXPEVT_RESET_TLB_MULTI_HIT, 0, 0); |
292 |
} else { |
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if ((cpu->cd.sh.utlb_lo[e] & SH4_PTEL_SZ_MASK) == |
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SH4_PTEL_SZ_4K) { |
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safe_to_invalidate = 1; |
296 |
vaddr_to_invalidate = |
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cpu->cd.sh.utlb_hi[e] & ~0xfff; |
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} |
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|
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cpu->cd.sh.utlb_hi[e] &= |
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~(SH4_PTEH_VPN_MASK | SH4_PTEH_ASID_MASK); |
302 |
cpu->cd.sh.utlb_hi[e] |= (idata & |
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(SH4_UTLB_AA_VPN_MASK | SH4_UTLB_AA_ASID_MASK)); |
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|
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cpu->cd.sh.utlb_lo[e] &= ~(SH4_PTEL_D | SH4_PTEL_V); |
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if (idata & SH4_UTLB_AA_D) |
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cpu->cd.sh.utlb_lo[e] |= SH4_PTEL_D; |
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if (idata & SH4_UTLB_AA_V) |
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cpu->cd.sh.utlb_lo[e] |= SH4_PTEL_V; |
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} |
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|
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if (safe_to_invalidate) |
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cpu->invalidate_translation_caches(cpu, |
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vaddr_to_invalidate, INVALIDATE_VADDR); |
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else |
316 |
cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL); |
317 |
} else { |
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odata = cpu->cd.sh.utlb_hi[e] & |
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(SH4_UTLB_AA_VPN_MASK | SH4_UTLB_AA_ASID_MASK); |
320 |
if (cpu->cd.sh.utlb_lo[e] & SH4_PTEL_D) |
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odata |= SH4_UTLB_AA_D; |
322 |
if (cpu->cd.sh.utlb_lo[e] & SH4_PTEL_V) |
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odata |= SH4_UTLB_AA_V; |
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memory_writemax64(cpu, data, len, odata); |
325 |
} |
326 |
|
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return 1; |
328 |
} |
329 |
|
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|
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DEVICE_ACCESS(sh4_utlb_da1) |
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{ |
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uint32_t mask = SH4_PTEL_WT | SH4_PTEL_SH | SH4_PTEL_D | SH4_PTEL_C |
334 |
| SH4_PTEL_SZ_MASK | SH4_PTEL_PR_MASK | SH4_PTEL_V | 0x1ffffc00; |
335 |
uint64_t idata = 0, odata = 0; |
336 |
int e = (relative_addr & SH4_UTLB_E_MASK) >> SH4_UTLB_E_SHIFT; |
337 |
|
338 |
if (relative_addr & 0x800000) { |
339 |
fatal("sh4_utlb_da1: TODO: da2 area\n"); |
340 |
exit(1); |
341 |
} |
342 |
|
343 |
if (writeflag == MEM_WRITE) { |
344 |
int safe_to_invalidate = 0; |
345 |
if ((cpu->cd.sh.utlb_lo[e] & SH4_PTEL_SZ_MASK)==SH4_PTEL_SZ_4K) |
346 |
safe_to_invalidate = 1; |
347 |
|
348 |
idata = memory_readmax64(cpu, data, len); |
349 |
cpu->cd.sh.utlb_lo[e] &= ~mask; |
350 |
cpu->cd.sh.utlb_lo[e] |= (idata & mask); |
351 |
|
352 |
if (safe_to_invalidate) |
353 |
cpu->invalidate_translation_caches(cpu, |
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cpu->cd.sh.utlb_hi[e] & ~0xfff, INVALIDATE_VADDR); |
355 |
else |
356 |
cpu->invalidate_translation_caches(cpu, |
357 |
0, INVALIDATE_ALL); |
358 |
} else { |
359 |
odata = cpu->cd.sh.utlb_lo[e] & mask; |
360 |
memory_writemax64(cpu, data, len, odata); |
361 |
} |
362 |
|
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return 1; |
364 |
} |
365 |
|
366 |
|
367 |
DEVICE_ACCESS(sh4) |
368 |
{ |
369 |
struct sh4_data *d = (struct sh4_data *) extra; |
370 |
uint64_t idata = 0, odata = 0; |
371 |
int timer_nr = 0; |
372 |
|
373 |
if (writeflag == MEM_WRITE) |
374 |
idata = memory_readmax64(cpu, data, len); |
375 |
|
376 |
relative_addr += SH4_REG_BASE; |
377 |
|
378 |
switch (relative_addr) { |
379 |
|
380 |
/*************************************************/ |
381 |
|
382 |
case SH4_PVR_ADDR: |
383 |
odata = cpu->cd.sh.cpu_type.pvr; |
384 |
break; |
385 |
|
386 |
case SH4_PRR_ADDR: |
387 |
odata = cpu->cd.sh.cpu_type.prr; |
388 |
break; |
389 |
|
390 |
case SH4_PTEH: |
391 |
if (writeflag == MEM_READ) |
392 |
odata = cpu->cd.sh.pteh; |
393 |
else { |
394 |
int old_asid = cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK; |
395 |
cpu->cd.sh.pteh = idata; |
396 |
|
397 |
if ((idata & SH4_PTEH_ASID_MASK) != old_asid) { |
398 |
/* TODO: Don't invalidate everything? */ |
399 |
cpu->invalidate_translation_caches( |
400 |
cpu, 0, INVALIDATE_ALL); |
401 |
} |
402 |
} |
403 |
break; |
404 |
|
405 |
case SH4_PTEL: |
406 |
if (writeflag == MEM_READ) |
407 |
odata = cpu->cd.sh.ptel; |
408 |
else |
409 |
cpu->cd.sh.ptel = idata; |
410 |
break; |
411 |
|
412 |
case SH4_TTB: |
413 |
if (writeflag == MEM_READ) |
414 |
odata = cpu->cd.sh.ttb; |
415 |
else |
416 |
cpu->cd.sh.ttb = idata; |
417 |
break; |
418 |
|
419 |
case SH4_TEA: |
420 |
if (writeflag == MEM_READ) |
421 |
odata = cpu->cd.sh.tea; |
422 |
else |
423 |
cpu->cd.sh.tea = idata; |
424 |
break; |
425 |
|
426 |
case SH4_PTEA: |
427 |
if (writeflag == MEM_READ) |
428 |
odata = cpu->cd.sh.ptea; |
429 |
else |
430 |
cpu->cd.sh.ptea = idata; |
431 |
break; |
432 |
|
433 |
case SH4_MMUCR: |
434 |
if (writeflag == MEM_READ) { |
435 |
odata = cpu->cd.sh.mmucr; |
436 |
} else { |
437 |
if (idata & SH4_MMUCR_TI) { |
438 |
/* TLB invalidate. */ |
439 |
|
440 |
/* TODO: Only invalidate something specific? |
441 |
And not everything? */ |
442 |
cpu->invalidate_translation_caches(cpu, |
443 |
0, INVALIDATE_ALL); |
444 |
|
445 |
/* Should always read back as 0. */ |
446 |
idata &= ~SH4_MMUCR_TI; |
447 |
} |
448 |
|
449 |
cpu->cd.sh.mmucr = idata; |
450 |
} |
451 |
break; |
452 |
|
453 |
case SH4_CCR: |
454 |
if (writeflag == MEM_READ) { |
455 |
odata = cpu->cd.sh.ccr; |
456 |
} else { |
457 |
cpu->cd.sh.ccr = idata; |
458 |
} |
459 |
break; |
460 |
|
461 |
case SH4_QACR0: |
462 |
if (writeflag == MEM_READ) { |
463 |
odata = cpu->cd.sh.qacr0; |
464 |
} else { |
465 |
cpu->cd.sh.qacr0 = idata; |
466 |
} |
467 |
break; |
468 |
|
469 |
case SH4_QACR1: |
470 |
if (writeflag == MEM_READ) { |
471 |
odata = cpu->cd.sh.qacr1; |
472 |
} else { |
473 |
cpu->cd.sh.qacr1 = idata; |
474 |
} |
475 |
break; |
476 |
|
477 |
case SH4_TRA: |
478 |
if (writeflag == MEM_READ) |
479 |
odata = cpu->cd.sh.tra; |
480 |
else |
481 |
cpu->cd.sh.tra = idata; |
482 |
break; |
483 |
|
484 |
case SH4_EXPEVT: |
485 |
if (writeflag == MEM_READ) |
486 |
odata = cpu->cd.sh.expevt; |
487 |
else |
488 |
cpu->cd.sh.expevt = idata; |
489 |
break; |
490 |
|
491 |
case SH4_INTEVT: |
492 |
if (writeflag == MEM_READ) |
493 |
odata = cpu->cd.sh.intevt; |
494 |
else |
495 |
cpu->cd.sh.intevt = idata; |
496 |
break; |
497 |
|
498 |
|
499 |
/********************************/ |
500 |
/* UBC: User Break Controller */ |
501 |
|
502 |
case 0xff200008: /* SH4_BBRA */ |
503 |
/* TODO */ |
504 |
break; |
505 |
|
506 |
|
507 |
/********************************/ |
508 |
/* TMU: Timer Management Unit */ |
509 |
|
510 |
case SH4_TOCR: |
511 |
/* Timer Output Control Register */ |
512 |
if (writeflag == MEM_WRITE) { |
513 |
d->tocr = idata; |
514 |
if (idata & TOCR_TCOE) |
515 |
fatal("[ sh4 timer: TCOE not yet " |
516 |
"implemented ]\n"); |
517 |
} else { |
518 |
odata = d->tocr; |
519 |
} |
520 |
break; |
521 |
|
522 |
case SH4_TSTR: |
523 |
/* Timer Start Register */ |
524 |
if (writeflag == MEM_READ) { |
525 |
odata = d->tstr; |
526 |
} else { |
527 |
if (idata & 1 && !(d->tstr & 1)) |
528 |
debug("[ sh4 timer: starting timer 0 ]\n"); |
529 |
if (idata & 2 && !(d->tstr & 2)) |
530 |
debug("[ sh4 timer: starting timer 1 ]\n"); |
531 |
if (idata & 4 && !(d->tstr & 4)) |
532 |
debug("[ sh4 timer: starting timer 2 ]\n"); |
533 |
if (!(idata & 1) && d->tstr & 1) |
534 |
debug("[ sh4 timer: stopping timer 0 ]\n"); |
535 |
if (!(idata & 2) && d->tstr & 2) |
536 |
debug("[ sh4 timer: stopping timer 1 ]\n"); |
537 |
if (!(idata & 4) && d->tstr & 4) |
538 |
debug("[ sh4 timer: stopping timer 2 ]\n"); |
539 |
d->tstr = idata; |
540 |
} |
541 |
break; |
542 |
|
543 |
case SH4_TCOR2: |
544 |
timer_nr ++; |
545 |
case SH4_TCOR1: |
546 |
timer_nr ++; |
547 |
case SH4_TCOR0: |
548 |
/* Timer Constant Register */ |
549 |
if (writeflag == MEM_READ) |
550 |
odata = d->tcor[timer_nr]; |
551 |
else |
552 |
d->tcor[timer_nr] = idata; |
553 |
break; |
554 |
|
555 |
case SH4_TCNT2: |
556 |
timer_nr ++; |
557 |
case SH4_TCNT1: |
558 |
timer_nr ++; |
559 |
case SH4_TCNT0: |
560 |
/* Timer Counter Register */ |
561 |
if (writeflag == MEM_READ) |
562 |
odata = d->tcnt[timer_nr]; |
563 |
else |
564 |
d->tcnt[timer_nr] = idata; |
565 |
break; |
566 |
|
567 |
case SH4_TCR2: |
568 |
timer_nr ++; |
569 |
case SH4_TCR1: |
570 |
timer_nr ++; |
571 |
case SH4_TCR0: |
572 |
/* Timer Control Register */ |
573 |
if (writeflag == MEM_READ) { |
574 |
odata = d->tcr[timer_nr]; |
575 |
} else { |
576 |
if (cpu->cd.sh.pclock == 0) { |
577 |
fatal("INTERNAL ERROR: pclock must be set" |
578 |
" for this machine. Aborting.\n"); |
579 |
exit(1); |
580 |
} |
581 |
|
582 |
switch (idata & 3) { |
583 |
case TCR_TPSC_P4: |
584 |
d->timer_hz[timer_nr] = cpu->cd.sh.pclock/4.0; |
585 |
break; |
586 |
case TCR_TPSC_P16: |
587 |
d->timer_hz[timer_nr] = cpu->cd.sh.pclock/16.0; |
588 |
break; |
589 |
case TCR_TPSC_P64: |
590 |
d->timer_hz[timer_nr] = cpu->cd.sh.pclock/64.0; |
591 |
break; |
592 |
case TCR_TPSC_P256: |
593 |
d->timer_hz[timer_nr] = cpu->cd.sh.pclock/256.0; |
594 |
break; |
595 |
} |
596 |
|
597 |
debug("[ sh4 timer %i clock set to %f Hz ]\n", |
598 |
timer_nr, d->timer_hz[timer_nr]); |
599 |
|
600 |
if (idata & (TCR_ICPF | TCR_ICPE1 | TCR_ICPE0 | |
601 |
TCR_CKEG1 | TCR_CKEG0 | TCR_TPSC2)) { |
602 |
fatal("Unimplemented SH4 timer control" |
603 |
" bits: 0x%08"PRIx32". Aborting.\n", |
604 |
(int) idata); |
605 |
exit(1); |
606 |
} |
607 |
|
608 |
if (d->tcr[timer_nr] & TCR_UNF && !(idata & TCR_UNF)) { |
609 |
cpu_interrupt_ack(cpu, SH_INTEVT_TMU0_TUNI0 |
610 |
+ 0x20 * timer_nr); |
611 |
if (d->timer_interrupts_pending[timer_nr] > 0) |
612 |
d->timer_interrupts_pending[timer_nr]--; |
613 |
} |
614 |
|
615 |
d->tcr[timer_nr] = idata; |
616 |
} |
617 |
break; |
618 |
|
619 |
|
620 |
/*************************************************/ |
621 |
/* BSC: Bus State Controller */ |
622 |
|
623 |
case SH4_RFCR: |
624 |
/* TODO */ |
625 |
fatal("[ SH4_RFCR: TODO ]\n"); |
626 |
odata = 0x11; |
627 |
break; |
628 |
|
629 |
#if 0 |
630 |
case SH4_UNKNOWN_2C: |
631 |
/* Not really part of the BSC? The 2C and 30 registers |
632 |
have to do with I/O pins... TODO */ |
633 |
/* |
634 |
* TODO: Perhaps this isn't actually part of the Bus State |
635 |
* controller? Marcus Comstedt's video.s tutorial on |
636 |
* how to output video on the Dreamcast indicates that |
637 |
* this is a way to sense which video cable is |
638 |
* connected. |
639 |
*/ |
640 |
if (writeflag == MEM_WRITE) { |
641 |
d->unknown_2c = idata; |
642 |
d->unknown_30 = idata; |
643 |
} else |
644 |
odata = d->unknown_2c; |
645 |
break; |
646 |
#endif |
647 |
|
648 |
#if 1 |
649 |
case SH4_UNKNOWN_30: |
650 |
if (writeflag == MEM_WRITE) |
651 |
d->unknown_30 = idata; |
652 |
else { |
653 |
odata = d->unknown_30; |
654 |
|
655 |
/* SUPER-UGLY HACK! TODO */ |
656 |
d->unknown_30 ++; |
657 |
} |
658 |
break; |
659 |
#endif |
660 |
|
661 |
|
662 |
/*********************************/ |
663 |
/* INTC: Interrupt Controller */ |
664 |
|
665 |
case SH4_ICR: |
666 |
if (writeflag == MEM_WRITE) { |
667 |
if (idata & 0x80) { |
668 |
fatal("SH4 INTC: IRLM not yet " |
669 |
"supported. TODO\n"); |
670 |
exit(1); |
671 |
} |
672 |
} |
673 |
break; |
674 |
|
675 |
case SH4_IPRA: |
676 |
if (writeflag == MEM_READ) |
677 |
odata = cpu->cd.sh.intc_ipra; |
678 |
else |
679 |
cpu->cd.sh.intc_ipra = idata; |
680 |
break; |
681 |
|
682 |
case SH4_IPRB: |
683 |
if (writeflag == MEM_READ) |
684 |
odata = cpu->cd.sh.intc_iprb; |
685 |
else |
686 |
cpu->cd.sh.intc_iprb = idata; |
687 |
break; |
688 |
|
689 |
case SH4_IPRC: |
690 |
if (writeflag == MEM_READ) |
691 |
odata = cpu->cd.sh.intc_iprc; |
692 |
else |
693 |
cpu->cd.sh.intc_iprc = idata; |
694 |
break; |
695 |
|
696 |
|
697 |
/*************************************************/ |
698 |
/* SCIF: Serial Controller Interface with FIFO */ |
699 |
|
700 |
case SH4_SCIF_BASE + SCIF_FTDR: |
701 |
if (writeflag == MEM_WRITE) |
702 |
console_putchar(d->scif_console_handle, idata); |
703 |
break; |
704 |
|
705 |
case SH4_SCIF_BASE + SCIF_SSR: |
706 |
/* TODO: Implement more of this. */ |
707 |
odata = SCSSR2_TDFE | SCSSR2_TEND; |
708 |
if (console_charavail(d->scif_console_handle)) |
709 |
odata |= SCSSR2_DR; |
710 |
break; |
711 |
|
712 |
case SH4_SCIF_BASE + SCIF_FRDR: |
713 |
{ |
714 |
int x = console_readchar(d->scif_console_handle); |
715 |
if (x == 13) |
716 |
x = 10; |
717 |
odata = x < 0? 0 : x; |
718 |
} |
719 |
break; |
720 |
|
721 |
case SH4_SCIF_BASE + SCIF_FDR: |
722 |
odata = console_charavail(d->scif_console_handle); |
723 |
break; |
724 |
|
725 |
/*************************************************/ |
726 |
|
727 |
default:if (writeflag == MEM_READ) { |
728 |
fatal("[ sh4: read from addr 0x%x ]\n", |
729 |
(int)relative_addr); |
730 |
} else { |
731 |
fatal("[ sh4: write to addr 0x%x: 0x%x ]\n", |
732 |
(int)relative_addr, (int)idata); |
733 |
} |
734 |
} |
735 |
|
736 |
if (writeflag == MEM_READ) |
737 |
memory_writemax64(cpu, data, len, odata); |
738 |
|
739 |
return 1; |
740 |
} |
741 |
|
742 |
|
743 |
DEVINIT(sh4) |
744 |
{ |
745 |
struct machine *machine = devinit->machine; |
746 |
struct sh4_data *d = malloc(sizeof(struct sh4_data)); |
747 |
if (d == NULL) { |
748 |
fprintf(stderr, "out of memory\n"); |
749 |
exit(1); |
750 |
} |
751 |
memset(d, 0, sizeof(struct sh4_data)); |
752 |
|
753 |
d->scif_console_handle = console_start_slave(devinit->machine, |
754 |
"SH4 SCIF", 1); |
755 |
|
756 |
memory_device_register(machine->memory, devinit->name, |
757 |
SH4_REG_BASE, 0x01000000, dev_sh4_access, d, DM_DEFAULT, NULL); |
758 |
|
759 |
/* On-chip RAM/cache: */ |
760 |
dev_ram_init(machine, 0x1e000000, 0x8000, DEV_RAM_RAM, 0x0); |
761 |
|
762 |
/* 0xe0000000: Store queues: */ |
763 |
dev_ram_init(machine, 0xe0000000, 32 * 2, DEV_RAM_RAM, 0x0); |
764 |
|
765 |
/* |
766 |
* 0xf0000000 SH4_CCIA I-Cache address array |
767 |
* 0xf1000000 SH4_CCID I-Cache data array |
768 |
* 0xf4000000 SH4_CCDA D-Cache address array |
769 |
* 0xf5000000 SH4_CCDD D-Cache data array |
770 |
* |
771 |
* TODO: Implement more correct cache behaviour? |
772 |
*/ |
773 |
dev_ram_init(machine, SH4_CCIA, SH4_ICACHE_SIZE, DEV_RAM_RAM, 0x0); |
774 |
dev_ram_init(machine, SH4_CCID, SH4_ICACHE_SIZE, DEV_RAM_RAM, 0x0); |
775 |
dev_ram_init(machine, SH4_CCDA, SH4_DCACHE_SIZE, DEV_RAM_RAM, 0x0); |
776 |
dev_ram_init(machine, SH4_CCDD, SH4_DCACHE_SIZE, DEV_RAM_RAM, 0x0); |
777 |
|
778 |
/* 0xf2000000 SH4_ITLB_AA */ |
779 |
memory_device_register(machine->memory, devinit->name, SH4_ITLB_AA, |
780 |
0x01000000, dev_sh4_itlb_aa_access, d, DM_DEFAULT, NULL); |
781 |
|
782 |
/* 0xf3000000 SH4_ITLB_DA1 */ |
783 |
memory_device_register(machine->memory, devinit->name, SH4_ITLB_DA1, |
784 |
0x01000000, dev_sh4_itlb_da1_access, d, DM_DEFAULT, NULL); |
785 |
|
786 |
/* 0xf6000000 SH4_UTLB_AA */ |
787 |
memory_device_register(machine->memory, devinit->name, SH4_UTLB_AA, |
788 |
0x01000000, dev_sh4_utlb_aa_access, d, DM_DEFAULT, NULL); |
789 |
|
790 |
/* 0xf7000000 SH4_UTLB_DA1 */ |
791 |
memory_device_register(machine->memory, devinit->name, SH4_UTLB_DA1, |
792 |
0x01000000, dev_sh4_utlb_da1_access, d, DM_DEFAULT, NULL); |
793 |
|
794 |
d->sh4_timer = timer_add(SH4_PSEUDO_TIMER_HZ, sh4_timer_tick, d); |
795 |
machine_add_tickfunction(devinit->machine, dev_sh4_tick, d, |
796 |
SH4_TICK_SHIFT, 0.0); |
797 |
|
798 |
/* Initial Timer values, according to the SH7750 manual: */ |
799 |
d->tcor[0] = 0xffffffff; d->tcnt[0] = 0xffffffff; |
800 |
d->tcor[1] = 0xffffffff; d->tcnt[1] = 0xffffffff; |
801 |
d->tcor[2] = 0xffffffff; d->tcnt[2] = 0xffffffff; |
802 |
|
803 |
return 1; |
804 |
} |
805 |
|