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/* |
/* |
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* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_sgi_mardigras.c,v 1.22 2006/02/09 20:02:59 debug Exp $ |
* $Id: dev_sgi_mardigras.c,v 1.25 2007/06/15 19:57:34 debug Exp $ |
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* |
* |
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* "MardiGras" graphics controller on SGI IP30 (Octane). |
* COMMENT: MardiGras graphics controller on SGI IP30 (Octane) |
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* |
* |
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* Most of this is just guesses based on the behaviour of Linux/Octane. |
* Most of this is just guesses based on the behaviour of Linux/Octane. |
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* |
* |
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return; |
return; |
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} |
} |
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debug("mardigras_20400(): 0x%016llx\n", (long long)idata); |
debug("mardigras_20400(): 0x%016"PRIx64"\n", (uint64_t) idata); |
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} |
} |
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/* |
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* dev_sgi_mardigras_access(): |
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*/ |
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DEVICE_ACCESS(sgi_mardigras) |
DEVICE_ACCESS(sgi_mardigras) |
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{ |
{ |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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} |
} |
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switch (relative_addr) { |
switch (relative_addr) { |
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case 0x00004: |
case 0x00004: |
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/* xtalk data: (according to Linux/IP30) */ |
/* xtalk data: (according to Linux/IP30) */ |
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/* (mfgr & 0x7ff) << 1 */ |
/* (mfgr & 0x7ff) << 1 */ |
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/* (rev & 0xf) << 28 */ |
/* (rev & 0xf) << 28 */ |
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odata = (2 << 28) | (0xc003 << 12) | (0x2aa << 1); |
odata = (2 << 28) | (0xc003 << 12) | (0x2aa << 1); |
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break; |
break; |
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case 0x20008: /* Fifo status */ |
case 0x20008: /* Fifo status */ |
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break; |
break; |
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case 0x20200: |
case 0x20200: |
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break; |
break; |
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case 0x20400: |
case 0x20400: |
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
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mardigras_20400(cpu, d, idata); |
mardigras_20400(cpu, d, idata); |
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else |
else |
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debug("[ sgi_mardigras: read from 0x20400? ]\n"); |
debug("[ sgi_mardigras: read from 0x20400? ]\n"); |
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break; |
break; |
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case 0x58040: |
case 0x58040: |
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/* HQ4 microcode stuff */ |
/* HQ4 microcode stuff */ |
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break; |
break; |
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case 0x70c30: |
case 0x70c30: |
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/* Palette register select? */ |
/* Palette register select? */ |
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
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else |
else |
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odata = d->palette_reg_select; |
odata = d->palette_reg_select; |
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break; |
break; |
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case 0x70d18: |
case 0x70d18: |
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/* Palette register read/write? */ |
/* Palette register read/write? */ |
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i = 3 * ((d->palette_reg_select >> 8) & 0xff); |
i = 3 * ((d->palette_reg_select >> 8) & 0xff); |
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(d->fb->rgb_palette[i+2] << 8); |
(d->fb->rgb_palette[i+2] << 8); |
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} |
} |
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break; |
break; |
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case 0x71208: |
case 0x71208: |
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odata = 8; |
odata = 8; |
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break; |
break; |
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default: |
default: |
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if (writeflag==MEM_READ) { |
if (writeflag==MEM_READ) { |
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debug("[ sgi_mardigras: read from 0x%08lx ]\n", |
debug("[ sgi_mardigras: read from 0x%08lx ]\n", |
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(long)relative_addr); |
(long)relative_addr); |
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} else { |
} else { |
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debug("[ sgi_mardigras: write to 0x%08lx: 0x%016llx" |
debug("[ sgi_mardigras: write to 0x%08lx: 0x%016"PRIx64 |
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" ]\n", (long)relative_addr, (long long)idata); |
" ]\n", (long) relative_addr, (uint64_t) idata); |
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} |
} |
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} |
} |
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{ |
{ |
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struct sgi_mardigras_data *d; |
struct sgi_mardigras_data *d; |
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d = malloc(sizeof(struct sgi_mardigras_data)); |
CHECK_ALLOCATION(d = malloc(sizeof(struct sgi_mardigras_data))); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct sgi_mardigras_data)); |
memset(d, 0, sizeof(struct sgi_mardigras_data)); |
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d->fb = dev_fb_init(devinit->machine, devinit->machine->memory, |
d->fb = dev_fb_init(devinit->machine, devinit->machine->memory, |