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/* |
/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_sgi_ip32.c,v 1.38 2005/11/21 09:17:27 debug Exp $ |
* $Id: dev_sgi_ip32.c,v 1.44 2006/01/01 13:17:17 debug Exp $ |
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* |
* |
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* SGI IP32 devices. |
* SGI IP32 devices. |
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* |
* |
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/* |
/* |
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* dev_crime_access(): |
* dev_crime_access(): |
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*/ |
*/ |
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int dev_crime_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(crime) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
|
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{ |
{ |
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struct crime_data *d = extra; |
struct crime_data *d = extra; |
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uint64_t idata = 0; |
uint64_t idata = 0; |
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int i; |
size_t i; |
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|
|
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
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idata &= ~0x200; |
idata &= ~0x200; |
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} |
} |
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if (idata & 0x800) { |
if (idata & 0x800) { |
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int j; |
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|
|
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/* This is used by the IP32 PROM's |
/* This is used by the IP32 PROM's |
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"reboot" command: */ |
"reboot" command: */ |
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for (i=0; i<cpu->machine->ncpus; i++) |
for (j=0; j<cpu->machine->ncpus; j++) |
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cpu->machine->cpus[i]->running = 0; |
cpu->machine->cpus[j]->running = 0; |
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cpu->machine-> |
cpu->machine-> |
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exit_without_entering_debugger = 1; |
exit_without_entering_debugger = 1; |
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idata &= ~0x800; |
idata &= ~0x800; |
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/* |
/* |
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* dev_mace_access(): |
* dev_mace_access(): |
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*/ |
*/ |
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int dev_mace_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(mace) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
|
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int writeflag, void *extra) |
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{ |
{ |
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int i; |
size_t i; |
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struct mace_data *d = extra; |
struct mace_data *d = extra; |
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|
|
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
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/* |
/* |
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* dev_macepci_access(): |
* dev_macepci_access(): |
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*/ |
*/ |
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int dev_macepci_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(macepci) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
|
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int writeflag, void *extra) |
|
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{ |
{ |
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struct macepci_data *d = (struct macepci_data *) extra; |
struct macepci_data *d = (struct macepci_data *) extra; |
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uint64_t idata = 0, odata=0; |
uint64_t idata = 0, odata=0; |
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int regnr, res = 1; |
int regnr, res = 1, bus, dev, func, pcireg; |
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|
|
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
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|
|
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/* Read from/write to the macepci: */ |
/* Read from/write to the macepci: */ |
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switch (relative_addr) { |
switch (relative_addr) { |
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|
|
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case 0x00: /* Error address */ |
case 0x00: /* Error address */ |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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} else { |
} else { |
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odata = 0; |
odata = 0; |
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} |
} |
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break; |
break; |
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|
|
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case 0x04: /* Error flags */ |
case 0x04: /* Error flags */ |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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} else { |
} else { |
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odata = 0x06; |
odata = 0x06; |
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} |
} |
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break; |
break; |
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|
|
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case 0x0c: /* Revision number */ |
case 0x0c: /* Revision number */ |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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} else { |
} else { |
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odata = 0x01; |
odata = 0x01; |
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} |
} |
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break; |
break; |
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|
|
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case 0xcf8: /* PCI ADDR */ |
case 0xcf8: /* PCI ADDR */ |
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bus_pci_decompose_1(idata, &bus, &dev, &func, &pcireg); |
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, pcireg); |
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break; |
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|
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case 0xcfc: /* PCI DATA */ |
case 0xcfc: /* PCI DATA */ |
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if (writeflag == MEM_WRITE) { |
bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? |
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res = bus_pci_access(cpu, mem, relative_addr, |
&odata : &idata, len, writeflag); |
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&idata, len, writeflag, d->pci_data); |
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} else { |
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res = bus_pci_access(cpu, mem, relative_addr, |
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&odata, len, writeflag, d->pci_data); |
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} |
|
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break; |
break; |
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|
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default: |
default: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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debug("[ macepci: unimplemented write to address " |
debug("[ macepci: unimplemented write to address " |
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/* |
/* |
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* dev_macepci_init(): |
* dev_macepci_init(): |
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*/ |
*/ |
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struct pci_data *dev_macepci_init(struct memory *mem, uint64_t baseaddr, |
struct pci_data *dev_macepci_init(struct machine *machine, |
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int pciirq) |
struct memory *mem, uint64_t baseaddr, int pciirq) |
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{ |
{ |
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struct macepci_data *d = malloc(sizeof(struct macepci_data)); |
struct macepci_data *d = malloc(sizeof(struct macepci_data)); |
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if (d == NULL) { |
if (d == NULL) { |
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} |
} |
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memset(d, 0, sizeof(struct macepci_data)); |
memset(d, 0, sizeof(struct macepci_data)); |
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|
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d->pci_data = bus_pci_init(pciirq, 0,0, 0,0,0, 0,0,0); |
d->pci_data = bus_pci_init(machine, pciirq, 0,0, 0,0,0, 0,0,0); |
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|
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memory_device_register(mem, "macepci", baseaddr, DEV_MACEPCI_LENGTH, |
memory_device_register(mem, "macepci", baseaddr, DEV_MACEPCI_LENGTH, |
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dev_macepci_access, (void *)d, DM_DEFAULT, NULL); |
dev_macepci_access, (void *)d, DM_DEFAULT, NULL); |
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/* |
/* |
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* dev_sgi_mec_access(): |
* dev_sgi_mec_access(): |
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*/ |
*/ |
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int dev_sgi_mec_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(sgi_mec) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
|
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int writeflag, void *extra) |
|
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{ |
{ |
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struct sgi_mec_data *d = (struct sgi_mec_data *) extra; |
struct sgi_mec_data *d = (struct sgi_mec_data *) extra; |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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/* |
/* |
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* dev_sgi_ust_access(): |
* dev_sgi_ust_access(): |
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*/ |
*/ |
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int dev_sgi_ust_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(sgi_ust) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
|
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int writeflag, void *extra) |
|
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{ |
{ |
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struct sgi_ust_data *d = (struct sgi_ust_data *) extra; |
struct sgi_ust_data *d = (struct sgi_ust_data *) extra; |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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/* |
/* |
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* dev_sgi_mte_access(): |
* dev_sgi_mte_access(): |
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*/ |
*/ |
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int dev_sgi_mte_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(sgi_mte) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
|
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int writeflag, void *extra) |
|
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{ |
{ |
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struct sgi_mte_data *d = (struct sgi_mte_data *) extra; |
struct sgi_mte_data *d = (struct sgi_mte_data *) extra; |
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uint64_t first_addr, last_addr, zerobuflen, fill_addr, fill_len; |
uint64_t first_addr, last_addr, zerobuflen, fill_addr, fill_len; |
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uint32_t x2 = (d->reg[0x2074 / sizeof(uint32_t)] |
uint32_t x2 = (d->reg[0x2074 / sizeof(uint32_t)] |
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>> 16) & 0xfff; |
>> 16) & 0xfff; |
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uint32_t y2 = d->reg[0x2074 / sizeof(uint32_t)]& 0xfff; |
uint32_t y2 = d->reg[0x2074 / sizeof(uint32_t)]& 0xfff; |
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int y; |
uint32_t y; |
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|
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op >>= 24; |
op >>= 24; |
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|
|
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uint32_t x2 = (d->reg[0x2074 / sizeof(uint32_t)] |
uint32_t x2 = (d->reg[0x2074 / sizeof(uint32_t)] |
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>> 16) & 0xfff; |
>> 16) & 0xfff; |
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uint32_t y2 = d->reg[0x2074 / sizeof(uint32_t)]& 0xfff; |
uint32_t y2 = d->reg[0x2074 / sizeof(uint32_t)]& 0xfff; |
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int x,y; |
size_t x, y; |
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|
|
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if (x2 < x1) { |
if (x2 < x1) { |
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int tmp = x1; x1 = x2; x2 = tmp; |
int tmp = x1; x1 = x2; x2 = tmp; |
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} |
} |
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} |
} |
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if (x2-x1 <= 15) |
if (x2-x1 <= 15) |
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data <<= 16; |
data <<= 16; |
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|
|
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x=x1; y=y1; |
x=x1; y=y1; |
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while (x <= x2 && y <= y2) { |
while (x <= x2 && y <= y2) { |
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unsigned char buf = color; |
unsigned char buf = color; |