/[gxemul]/trunk/src/devices/dev_sgi_ip30.c
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Contents of /trunk/src/devices/dev_sgi_ip30.c

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 9519 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /*
2 * Copyright (C) 2004-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_sgi_ip30.c,v 1.20 2006/01/01 13:17:17 debug Exp $
29 *
30 * SGI IP30 stuff.
31 *
32 * This is just comprised of hardcoded guesses so far. (Ugly.)
33 */
34
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38
39 #include "cpu.h"
40 #include "devices.h"
41 #include "machine.h"
42 #include "memory.h"
43 #include "misc.h"
44
45
46 void dev_sgi_ip30_tick(struct cpu *cpu, void *extra)
47 {
48 struct sgi_ip30_data *d = extra;
49
50 d->reg_0x20000 += 1000;
51
52 if (d->imask0 & ((int64_t)1<<50)) {
53 /* TODO: Only interrupt if reg 0x20000 (the counter)
54 has passed the compare (0x30000). */
55 cpu_interrupt(cpu, 8+1 + 50);
56 }
57 }
58
59
60 /*
61 * dev_sgi_ip30_access():
62 */
63 DEVICE_ACCESS(sgi_ip30)
64 {
65 struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
66 uint64_t idata = 0, odata = 0;
67
68 if (writeflag == MEM_WRITE)
69 idata = memory_readmax64(cpu, data, len);
70
71 switch (relative_addr) {
72 case 0x20:
73 /* Memory bank configuration: */
74 odata = 0x80010000ULL;
75 break;
76 case 0x10000: /* Interrupt mask register 0: */
77 if (writeflag == MEM_WRITE) {
78 d->imask0 = idata;
79 } else {
80 odata = d->imask0;
81 }
82 break;
83 case 0x10018:
84 /*
85 * If this is not implemented, the IP30 PROM complains during
86 * bootup:
87 *
88 * *FAILED*
89 * Address: 0xffffffffaff10018, Expected:
90 * 0x0000000000000001, Received: 0x0000000000000000
91 */
92 if (writeflag == MEM_WRITE) {
93 d->reg_0x10018 = idata;
94 } else {
95 odata = d->reg_0x10018;
96 }
97 break;
98 case 0x10020: /* Set ISR, according to Linux/IP30 */
99 d->isr = idata;
100 /* Recalculate CPU interrupt assertions: */
101 cpu_interrupt(cpu, 8);
102 break;
103 case 0x10028: /* Clear ISR, according to Linux/IP30 */
104 d->isr &= ~idata;
105 /* Recalculate CPU interrupt assertions: */
106 cpu_interrupt(cpu, 8);
107 break;
108 case 0x10030: /* Interrupt Status Register */
109 if (writeflag == MEM_WRITE) {
110 /* Clear-on-write (TODO: is this correct?) */
111 d->isr &= ~idata;
112 /* Recalculate CPU interrupt assertions: */
113 cpu_interrupt(cpu, 8);
114 } else {
115 odata = d->isr;
116 }
117 break;
118 case 0x20000:
119 /* A counter */
120 if (writeflag == MEM_WRITE) {
121 d->reg_0x20000 = idata;
122 } else {
123 odata = d->reg_0x20000;
124 }
125 break;
126 case 0x30000:
127 if (writeflag == MEM_WRITE) {
128 d->reg_0x30000 = idata;
129 } else {
130 odata = d->reg_0x30000;
131 }
132 break;
133 default:
134 if (writeflag == MEM_WRITE) {
135 debug("[ sgi_ip30: unimplemented write to address "
136 "0x%x, data=0x%02x ]\n", (int)relative_addr,
137 (int)idata);
138 } else {
139 debug("[ sgi_ip30: unimplemented read from address"
140 " 0x%x ]\n", (int)relative_addr);
141 }
142 }
143
144 if (writeflag == MEM_READ)
145 memory_writemax64(cpu, data, len, odata);
146
147 return 1;
148 }
149
150
151 /*
152 * dev_sgi_ip30_2_access():
153 */
154 DEVICE_ACCESS(sgi_ip30_2)
155 {
156 struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
157 uint64_t idata = 0, odata = 0;
158
159 idata = memory_readmax64(cpu, data, len);
160
161 switch (relative_addr) {
162
163 /* 0x114 + 0x40 * (wid - 8): 0x80000000 for "alive",
164 according to Linux/IP30 */
165
166 case 0x114 + 0x40 * (12 - 8):
167 fatal("[ IP30: asdvasdvnb ]\n");
168 odata = 0x80000000;
169 break;
170
171 case 0x0029c:
172 /*
173 * If this is not implemented, the IP30 PROM complains during
174 * bootup:
175 *
176 * *FAILED*
177 * Address: 0xffffffffb000029c, Expected:
178 * 0x0000000000000001, Received: 0x0000000000000000
179 */
180 if (writeflag == MEM_WRITE) {
181 d->reg_0x0029c = idata;
182 } else {
183 odata = d->reg_0x0029c;
184 }
185 break;
186 default:
187 if (writeflag == MEM_WRITE) {
188 debug("[ sgi_ip30_2: unimplemented write to "
189 "address 0x%x, data=0x%02x ]\n",
190 (int)relative_addr, (int)idata);
191 } else {
192 debug("[ sgi_ip30_2: unimplemented read from address "
193 "0x%x ]\n", (int)relative_addr);
194 }
195 }
196
197 if (writeflag == MEM_READ)
198 memory_writemax64(cpu, data, len, odata);
199
200 return 1;
201 }
202
203
204 /*
205 * dev_sgi_ip30_3_access():
206 */
207 DEVICE_ACCESS(sgi_ip30_3)
208 {
209 struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
210 uint64_t idata = 0, odata = 0;
211
212 idata = memory_readmax64(cpu, data, len);
213
214 switch (relative_addr) {
215 case 0xb4:
216 if (writeflag == MEM_WRITE) {
217 debug("[ sgi_ip30_3: unimplemented write to "
218 "address 0x%x, data=0x%02x ]\n",
219 (int)relative_addr, (int)idata);
220 } else {
221 odata = 2; /* should be 2, or Irix loops */
222 }
223 break;
224 case 0x00104:
225 if (writeflag == MEM_WRITE) {
226 debug("[ sgi_ip30_3: unimplemented write to address "
227 "0x%x, data=0x%02x ]\n", (int)relative_addr,
228 (int)idata);
229 } else {
230 odata = 64; /* should be 64, or the PROM
231 complains */
232 }
233 break;
234 case 0x00284:
235 /*
236 * If this is not implemented, the IP30 PROM complains during
237 * bootup:
238 *
239 * *FAILED*
240 * Address: 0xffffffffbf000284, Expected:
241 * 0x0000000000000001, Received: 0x0000000000000000
242 */
243 if (writeflag == MEM_WRITE) {
244 d->reg_0x00284 = idata;
245 } else {
246 odata = d->reg_0x00284;
247 }
248 break;
249 default:
250 if (writeflag == MEM_WRITE) {
251 debug("[ sgi_ip30_3: unimplemented write to address "
252 "0x%x, data=0x%02x ]\n", (int)relative_addr,
253 (int)idata);
254 } else {
255 debug("[ sgi_ip30_3: unimplemented read from "
256 "address 0x%x ]\n", (int)relative_addr);
257 }
258 }
259
260 if (writeflag == MEM_READ)
261 memory_writemax64(cpu, data, len, odata);
262
263 return 1;
264 }
265
266
267 /*
268 * dev_sgi_ip30_4_access():
269 */
270 DEVICE_ACCESS(sgi_ip30_4)
271 {
272 struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
273 uint64_t idata = 0, odata = 0;
274
275 idata = memory_readmax64(cpu, data, len);
276
277 switch (relative_addr) {
278 case 0x000b0:
279 /*
280 * If this is not implemented, the IP30 PROM complains during
281 * bootup:
282 *
283 * *FAILED*
284 * Address: 0xffffffffbf6000b0, Expected:
285 * 0x0000000000000001, Received: 0x0000000000000000
286 */
287 if (writeflag == MEM_WRITE) {
288 d->reg_0x000b0 = idata;
289 } else {
290 odata = d->reg_0x000b0;
291 }
292 break;
293 default:
294 if (writeflag == MEM_WRITE) {
295 debug("[ sgi_ip30_4: unimplemented write to address"
296 " 0x%x, data=0x%02x ]\n",
297 (int)relative_addr, (int)idata);
298 } else {
299 debug("[ sgi_ip30_4: unimplemented read from address"
300 " 0x%x ]\n", (int)relative_addr);
301 }
302 }
303
304 if (writeflag == MEM_READ)
305 memory_writemax64(cpu, data, len, odata);
306
307 return 1;
308 }
309
310
311 /*
312 * dev_sgi_ip30_5_access():
313 */
314 DEVICE_ACCESS(sgi_ip30_5)
315 {
316 struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
317 uint64_t idata = 0, odata = 0;
318
319 idata = memory_readmax64(cpu, data, len);
320
321 switch (relative_addr) {
322 case 0x00000:
323 if (writeflag == MEM_WRITE) {
324 d->reg_0x00000 = idata;
325 } else {
326 odata = d->reg_0x00000;
327 }
328 break;
329 default:
330 if (writeflag == MEM_WRITE) {
331 debug("[ sgi_ip30_5: unimplemented write to address "
332 "0x%x, data=0x%02x ]\n", (int)relative_addr,
333 (int)idata);
334 } else {
335 debug("[ sgi_ip30_5: unimplemented read from address "
336 "0x%x ]\n", (int)relative_addr);
337 }
338 }
339
340 if (writeflag == MEM_READ)
341 memory_writemax64(cpu, data, len, odata);
342
343 return 1;
344 }
345
346
347 /*
348 * dev_sgi_ip30_init():
349 */
350 struct sgi_ip30_data *dev_sgi_ip30_init(struct machine *machine,
351 struct memory *mem, uint64_t baseaddr)
352 {
353 struct sgi_ip30_data *d = malloc(sizeof(struct sgi_ip30_data));
354 if (d == NULL) {
355 fprintf(stderr, "out of memory\n");
356 exit(1);
357 }
358 memset(d, 0, sizeof(struct sgi_ip30_data));
359
360 memory_device_register(mem, "sgi_ip30_1", baseaddr,
361 DEV_SGI_IP30_LENGTH, dev_sgi_ip30_access, (void *)d,
362 DM_DEFAULT, NULL);
363 memory_device_register(mem, "sgi_ip30_2", 0x10000000,
364 0x10000, dev_sgi_ip30_2_access, (void *)d, DM_DEFAULT, NULL);
365 memory_device_register(mem, "sgi_ip30_3", 0x1f000000,
366 0x10000, dev_sgi_ip30_3_access, (void *)d, DM_DEFAULT, NULL);
367 memory_device_register(mem, "sgi_ip30_4", 0x1f600000,
368 0x10000, dev_sgi_ip30_4_access, (void *)d, DM_DEFAULT, NULL);
369 memory_device_register(mem, "sgi_ip30_5", 0x1f6c0000,
370 0x10000, dev_sgi_ip30_5_access, (void *)d, DM_DEFAULT, NULL);
371
372 machine_add_tickfunction(machine, dev_sgi_ip30_tick, d, 16);
373
374 return d;
375 }
376

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