/[gxemul]/trunk/src/devices/dev_sgi_ip22.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/devices/dev_sgi_ip22.c

Parent Directory Parent Directory | Revision Log Revision Log


Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 12682 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 /*
2 * Copyright (C) 2004-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_sgi_ip22.c,v 1.30 2007/01/28 14:15:30 debug Exp $
29 *
30 * SGI IP22 stuff.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36
37 #include "cpu.h"
38 #include "devices.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42
43 #include "imcreg.h"
44
45
46 #define SGI_IP22_TICK_SHIFT 14
47
48
49 /*
50 * dev_sgi_ip22_tick():
51 */
52 void dev_sgi_ip22_tick(struct cpu *cpu, void *extra)
53 {
54 struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
55
56 if (d->reg[0x38 / 4] != 0)
57 d->reg[0x38 / 4] --;
58 }
59
60
61 /*
62 * dev_sgi_ip22_imc_access():
63 *
64 * The memory controller (?).
65 */
66 DEVICE_ACCESS(sgi_ip22_imc)
67 {
68 struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
69 uint64_t idata = 0, odata = 0;
70 int regnr;
71
72 if (writeflag == MEM_WRITE)
73 idata = memory_readmax64(cpu, data, len);
74
75 regnr = relative_addr / sizeof(uint32_t);
76
77 if (writeflag == MEM_WRITE)
78 d->imc_reg[regnr] = idata;
79 else
80 odata = d->imc_reg[regnr];
81
82 switch (relative_addr) {
83 case (IMC_CPUCTRL0 - IP22_IMC_BASE):
84 if (writeflag == MEM_WRITE) {
85 /* debug("[ sgi_ip22_imc: write to "
86 "IMC_CPUCTRL0, data=0x%08x ]\n", (int)idata); */
87 } else {
88 /* debug("[ sgi_ip22_imc: read from IMC_CPUCTRL0, "
89 "data=0x%08x ]\n", (int)odata); */
90 }
91 break;
92 case (IMC_SYSID - IP22_IMC_BASE):
93 if (writeflag == MEM_WRITE) {
94 debug("[ sgi_ip22_imc: unimplemented write "
95 "IMC_SYSID, data=0x%08x ]\n", (int)idata);
96 } else {
97 /* Lowest 4 bits are the revision bits. */
98 odata = 3; /* + IMC_SYSID_HAVEISA; */
99 /* debug("[ sgi_ip22_imc: read from IMC_SYSID, "
100 "data=0x%08x ]\n", (int)odata); */
101 }
102 break;
103 case (IMC_WDOG - IP22_IMC_BASE):
104 if (writeflag == MEM_WRITE) {
105 /* debug("[ sgi_ip22_imc: write to IMC_WDOG, "
106 "data=0x%08x ]\n", (int)idata); */
107 } else {
108 /* debug("[ sgi_ip22_imc: read from IMC_WDOG, "
109 "data=0x%08x ]\n", (int)odata); */
110 }
111 break;
112 case (IMC_MEMCFG0 - IP22_IMC_BASE):
113 if (writeflag == MEM_WRITE) {
114 debug("[ sgi_ip22_imc: unimplemented write "
115 "IMC_MEMCFG0, data=0x%08x ]\n", (int)idata);
116 } else {
117 odata = 0x3100 + (0x8000000 >> 22); /* ? TODO */
118 /* debug("[ sgi_ip22_imc: read from IMC_MEMCFG0,"
119 " data=0x%08x ]\n", (int)odata); */
120 }
121 break;
122 case (IMC_MEMCFG1 - IP22_IMC_BASE):
123 if (writeflag == MEM_WRITE) {
124 debug("[ sgi_ip22_imc: unimplemented write "
125 "IMC_MEMCFG1, data=0x%08x ]\n", (int)idata);
126 } else {
127 odata = 0;
128 /* debug("[ sgi_ip22_imc: read from IMC_MEMCFG1, "
129 "data=0x%08x ]\n", (int)odata); */
130 }
131 break;
132 case (IMC_EEPROM - IP22_IMC_BASE):
133 /*
134 * The IP22 prom tries to access this during bootup,
135 * but I have no idea how it works.
136 */
137 if (writeflag == MEM_WRITE) {
138 debug("[ sgi_ip22_imc: write to IMC_EEPROM, data="
139 "0x%08x ]\n", (int)idata);
140 } else {
141 odata = random() & 0x1e;
142 debug("[ sgi_ip22_imc: read from IMC_WDOG, "
143 "data=0x%08x ]\n", (int)odata);
144 }
145 break;
146 default:
147 if (writeflag == MEM_WRITE) {
148 debug("[ sgi_ip22_imc: unimplemented write to "
149 "address 0x%x, data=0x%08x ]\n",
150 (int)relative_addr, (int)idata);
151 } else {
152 debug("[ sgi_ip22_imc: unimplemented read from "
153 "address 0x%x, data=0x%08x ]\n",
154 (int)relative_addr, (int)odata);
155 }
156 }
157
158 if (writeflag == MEM_READ)
159 memory_writemax64(cpu, data, len, odata);
160
161 return 1;
162 }
163
164
165 /*
166 * dev_sgi_ip22_unknown_access():
167 *
168 * A so far unknown device, used by the IP22 prom during startup.
169 */
170 DEVICE_ACCESS(sgi_ip22_unknown)
171 {
172 struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
173 uint64_t idata = 0, odata = 0;
174
175 idata = memory_readmax64(cpu, data, len);
176
177 switch (relative_addr) {
178 case 0x04:
179 if (writeflag == MEM_WRITE) {
180 debug("[ sgi_ip22_unknown: write to address 0x%x,"
181 " data=0x%08x ]\n", (int)relative_addr, (int)idata);
182 } else {
183 odata = d->unknown_timer;
184 d->unknown_timer += 100;
185 debug("[ sgi_ip22_unknown: read from address 0x%x, "
186 "data=0x%08x ]\n", (int)relative_addr, (int)odata);
187 }
188 break;
189 default:
190 if (writeflag == MEM_WRITE) {
191 debug("[ sgi_ip22_unknown: unimplemented write to "
192 "address 0x%x, data=0x%08x ]\n",
193 (int)relative_addr, (int)idata);
194 } else {
195 debug("[ sgi_ip22_unknown: unimplemented read from "
196 "address 0x%x, data=0x%08x ]\n",
197 (int)relative_addr, (int)odata);
198 }
199 }
200
201 if (writeflag == MEM_READ)
202 memory_writemax64(cpu, data, len, odata);
203
204 return 1;
205 }
206
207
208 /*
209 * dev_sgi_ip22_unknown2_access():
210 *
211 * A so far unknown device, used by the IP22 prom during startup.
212 */
213 DEVICE_ACCESS(sgi_ip22_unknown2)
214 {
215 struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
216 uint64_t idata = 0, odata = 0;
217 int regnr;
218
219 idata = memory_readmax64(cpu, data, len);
220 regnr = relative_addr / sizeof(uint32_t);
221
222 if (writeflag == MEM_WRITE)
223 d->unknown2_reg[regnr] = idata;
224 else
225 odata = d->unknown2_reg[regnr];
226
227 switch (relative_addr) {
228 default:
229 if (writeflag == MEM_WRITE) {
230 debug("[ sgi_ip22_unknown2: unimplemented write "
231 "to address 0x%x, data=0x%08x ]\n",
232 (int)relative_addr, (int)idata);
233 } else {
234 debug("[ sgi_ip22_unknown2: unimplemented read from "
235 "address 0x%x, data=0x%08x ]\n",
236 (int)relative_addr, (int)odata);
237 }
238 }
239
240 if (writeflag == MEM_READ)
241 memory_writemax64(cpu, data, len, odata);
242
243 return 1;
244 }
245
246
247 /*
248 * dev_sgi_ip22_sysid_access():
249 */
250 DEVICE_ACCESS(sgi_ip22_sysid)
251 {
252 struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
253 uint64_t idata = 0, odata = 0;
254
255 idata = memory_readmax64(cpu, data, len);
256
257 if (writeflag == MEM_WRITE) {
258 debug("[ sgi_ip22_sysid: write to address 0x%x, "
259 "data=0x%08x ]\n", (int)relative_addr, (int)idata);
260 } else {
261 /*
262 * According to NetBSD's sgimips/ip22.c:
263 *
264 * printf("IOC rev %d, machine %s, board rev %d\n",
265 * (sysid >> 5) & 0x07,
266 * (sysid & 1) ? "Indigo2 (Fullhouse)" : "Indy (Guiness)",
267 * (sysid >> 1) & 0x0f);
268 */
269
270 /* IOC rev 1, Guiness, board rev 3: */
271 odata = (1 << 5) + (3 << 1) + (d->guiness_flag? 0 : 1);
272
273 debug("[ sgi_ip22_sysid: read from address 0x%x, data="
274 "0x%08x ]\n", (int)relative_addr, (int)odata);
275 }
276
277 if (writeflag == MEM_READ)
278 memory_writemax64(cpu, data, len, odata);
279
280 return 1;
281 }
282
283
284 /*
285 * dev_sgi_ip22_access():
286 */
287 DEVICE_ACCESS(sgi_ip22)
288 {
289 struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
290 uint64_t idata = 0, odata = 0;
291 int regnr;
292
293 idata = memory_readmax64(cpu, data, len);
294 regnr = relative_addr / sizeof(uint32_t);
295
296 if (writeflag == MEM_WRITE)
297 d->reg[regnr] = idata;
298 else
299 odata = d->reg[regnr];
300
301 /* Read from/write to the sgi_ip22: */
302 switch (relative_addr) {
303 case 0x00: /* local0 irq stat */
304 if (writeflag == MEM_WRITE) {
305 debug("[ sgi_ip22: write to local0 IRQ STAT, "
306 "data=0x%llx ]\n", (long long)idata);
307 } else {
308 debug("[ sgi_ip22: read from local0 IRQ STAT, "
309 "data=0x%llx ]\n", (long long)odata);
310 }
311 break;
312 case 0x04: /* local0 irq mask */
313 if (writeflag == MEM_WRITE) {
314 /*
315 * Ugly hack: if an interrupt is asserted, and someone
316 * writes to this mask register, the interrupt should
317 * be masked. That is, sgi_ip22_interrupt() in
318 * src/machine.c has to be called to deal with this.
319 * The ugly solution I choose here is to deassert
320 * some interrupt which should never be used anyway.
321 * (TODO: Fix this.)
322 */
323
324 fatal("TODO: ip22 legacy interrupt rewrite!\n");
325 abort();
326
327 // cpu_interrupt_ack(cpu, 8 + 63);
328 debug("[ sgi_ip22: write to local0 IRQ MASK, "
329 "data=0x%llx ]\n", (long long)idata);
330 } else {
331 debug("[ sgi_ip22: read from local0 IRQ MASK, "
332 "data=0x%llx ]\n", (long long)odata);
333 }
334 break;
335 case 0x08: /* local1 irq stat */
336 if (writeflag == MEM_WRITE) {
337 debug("[ sgi_ip22: write to local1 IRQ STAT, "
338 "data=0x%llx ]\n", (long long)idata);
339 } else {
340 debug("[ sgi_ip22: read from local1 IRQ STAT, "
341 "data=0x%llx ]\n", (long long)odata);
342 }
343 break;
344 case 0x0c: /* local1 irq mask */
345 if (writeflag == MEM_WRITE) {
346 /* See commen above, about local0 irq mask. */
347
348 fatal("TODO: ip22 legacy interrupt rewrite!\n");
349 abort();
350 // cpu_interrupt_ack(cpu, 8 + 63);
351 debug("[ sgi_ip22: write to local1 IRQ MASK, "
352 "data=0x%llx ]\n", (long long)idata);
353 } else {
354 debug("[ sgi_ip22: read from local1 IRQ MASK, "
355 "data=0x%llx ]\n", (long long)odata);
356 }
357 break;
358 case 0x10:
359 if (writeflag == MEM_WRITE) {
360 debug("[ sgi_ip22: write to mappable IRQ STAT, "
361 "data=0x%llx ]\n", (long long)idata);
362 } else {
363 debug("[ sgi_ip22: read from mappable IRQ STAT, "
364 "data=0x%llx ]\n", (long long)odata);
365 }
366 break;
367 case 0x14:
368 if (writeflag == MEM_WRITE) {
369 debug("[ sgi_ip22: write to mappable local0 IRQ "
370 "MASK, data=0x%llx ]\n", (long long)idata);
371 } else {
372 debug("[ sgi_ip22: read from mappable local0 IRQ "
373 "MASK, data=0x%llx ]\n", (long long)odata);
374 }
375 break;
376 case 0x18:
377 if (writeflag == MEM_WRITE) {
378 debug("[ sgi_ip22: write to mappable local1 IRQ "
379 "MASK, data=0x%llx ]\n", (long long)idata);
380 } else {
381 debug("[ sgi_ip22: read from mappable local1 IRQ "
382 "MASK, data=0x%llx ]\n", (long long)odata);
383 }
384 break;
385 case 0x38: /* timer count */
386 if (writeflag == MEM_WRITE) {
387 /* Two byte values are written to this address,
388 sequentially... TODO */
389 } else {
390 /* The timer is decreased by the tick function. */
391 }
392 break;
393 case 0x3b: /* ? */
394 odata = random();
395 break;
396 case 0x3c: /* timer control */
397 break;
398 case 0x3f: /* ? */
399 odata = random();
400 break;
401 default:
402 if (writeflag == MEM_WRITE) {
403 debug("[ sgi_ip22: unimplemented write to address "
404 "0x%x, data=0x%02x ]\n", (int)relative_addr,
405 (int)idata);
406 } else {
407 debug("[ sgi_ip22: unimplemented read from address "
408 "0x%llx ]\n", (long long)relative_addr);
409 }
410 }
411
412 if (writeflag == MEM_READ)
413 memory_writemax64(cpu, data, len, odata);
414
415 return 1;
416 }
417
418
419 /*
420 * dev_sgi_ip22_init():
421 */
422 struct sgi_ip22_data *dev_sgi_ip22_init(struct machine *machine,
423 struct memory *mem, uint64_t baseaddr, int guiness_flag)
424 {
425 struct sgi_ip22_data *d = malloc(sizeof(struct sgi_ip22_data));
426 if (d == NULL) {
427 fprintf(stderr, "out of memory\n");
428 exit(1);
429 }
430 memset(d, 0, sizeof(struct sgi_ip22_data));
431 d->guiness_flag = guiness_flag;
432
433 memory_device_register(mem, "sgi_ip22", baseaddr, DEV_SGI_IP22_LENGTH,
434 dev_sgi_ip22_access, (void *)d, DM_DEFAULT, NULL);
435 memory_device_register(mem, "sgi_ip22_sysid", 0x1fbd9858, 0x8,
436 dev_sgi_ip22_sysid_access, (void *)d, DM_DEFAULT, NULL);
437 memory_device_register(mem, "sgi_ip22_imc", IP22_IMC_BASE,
438 DEV_SGI_IP22_IMC_LENGTH, dev_sgi_ip22_imc_access, (void *)d,
439 DM_DEFAULT, NULL);
440 memory_device_register(mem, "sgi_ip22_unknown", 0x1fa01000, 0x10,
441 dev_sgi_ip22_unknown_access, (void *)d, DM_DEFAULT, NULL);
442 memory_device_register(mem, "sgi_ip22_unknown2", IP22_UNKNOWN2_BASE,
443 DEV_SGI_IP22_UNKNOWN2_LENGTH, dev_sgi_ip22_unknown2_access,
444 (void *)d, DM_DEFAULT, NULL);
445
446 machine_add_tickfunction(machine, dev_sgi_ip22_tick, d,
447 SGI_IP22_TICK_SHIFT, 0.0);
448
449 return d;
450 }
451

  ViewVC Help
Powered by ViewVC 1.1.26