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dpavlin |
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/* |
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dpavlin |
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* Copyright (C) 2004-2007 Anders Gavare. All rights reserved. |
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dpavlin |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: dev_sgi_ip22.c,v 1.33 2007/06/15 19:57:34 debug Exp $ |
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dpavlin |
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* |
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dpavlin |
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* COMMENT: SGI IP22 stuff |
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dpavlin |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "cpu.h" |
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#include "devices.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "imcreg.h" |
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#define SGI_IP22_TICK_SHIFT 14 |
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dpavlin |
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DEVICE_TICK(sgi_ip22) |
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dpavlin |
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{ |
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dpavlin |
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struct sgi_ip22_data *d = extra; |
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dpavlin |
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if (d->reg[0x38 / 4] != 0) |
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d->reg[0x38 / 4] --; |
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} |
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/* |
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* dev_sgi_ip22_imc_access(): |
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* |
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* The memory controller (?). |
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*/ |
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dpavlin |
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DEVICE_ACCESS(sgi_ip22_imc) |
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dpavlin |
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{ |
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dpavlin |
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struct sgi_ip22_data *d = extra; |
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dpavlin |
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uint64_t idata = 0, odata = 0; |
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int regnr; |
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dpavlin |
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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dpavlin |
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regnr = relative_addr / sizeof(uint32_t); |
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if (writeflag == MEM_WRITE) |
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d->imc_reg[regnr] = idata; |
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else |
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odata = d->imc_reg[regnr]; |
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switch (relative_addr) { |
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case (IMC_CPUCTRL0 - IP22_IMC_BASE): |
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if (writeflag == MEM_WRITE) { |
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/* debug("[ sgi_ip22_imc: write to " |
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"IMC_CPUCTRL0, data=0x%08x ]\n", (int)idata); */ |
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} else { |
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/* debug("[ sgi_ip22_imc: read from IMC_CPUCTRL0, " |
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"data=0x%08x ]\n", (int)odata); */ |
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} |
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break; |
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case (IMC_SYSID - IP22_IMC_BASE): |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_imc: unimplemented write " |
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"IMC_SYSID, data=0x%08x ]\n", (int)idata); |
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} else { |
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/* Lowest 4 bits are the revision bits. */ |
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odata = 3; /* + IMC_SYSID_HAVEISA; */ |
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/* debug("[ sgi_ip22_imc: read from IMC_SYSID, " |
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"data=0x%08x ]\n", (int)odata); */ |
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} |
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break; |
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case (IMC_WDOG - IP22_IMC_BASE): |
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if (writeflag == MEM_WRITE) { |
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/* debug("[ sgi_ip22_imc: write to IMC_WDOG, " |
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"data=0x%08x ]\n", (int)idata); */ |
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} else { |
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/* debug("[ sgi_ip22_imc: read from IMC_WDOG, " |
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"data=0x%08x ]\n", (int)odata); */ |
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} |
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break; |
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case (IMC_MEMCFG0 - IP22_IMC_BASE): |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_imc: unimplemented write " |
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"IMC_MEMCFG0, data=0x%08x ]\n", (int)idata); |
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} else { |
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odata = 0x3100 + (0x8000000 >> 22); /* ? TODO */ |
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/* debug("[ sgi_ip22_imc: read from IMC_MEMCFG0," |
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" data=0x%08x ]\n", (int)odata); */ |
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} |
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break; |
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case (IMC_MEMCFG1 - IP22_IMC_BASE): |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_imc: unimplemented write " |
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"IMC_MEMCFG1, data=0x%08x ]\n", (int)idata); |
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} else { |
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odata = 0; |
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/* debug("[ sgi_ip22_imc: read from IMC_MEMCFG1, " |
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"data=0x%08x ]\n", (int)odata); */ |
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} |
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break; |
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case (IMC_EEPROM - IP22_IMC_BASE): |
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/* |
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* The IP22 prom tries to access this during bootup, |
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* but I have no idea how it works. |
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*/ |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_imc: write to IMC_EEPROM, data=" |
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"0x%08x ]\n", (int)idata); |
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} else { |
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odata = random() & 0x1e; |
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debug("[ sgi_ip22_imc: read from IMC_WDOG, " |
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"data=0x%08x ]\n", (int)odata); |
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} |
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break; |
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default: |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_imc: unimplemented write to " |
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"address 0x%x, data=0x%08x ]\n", |
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(int)relative_addr, (int)idata); |
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} else { |
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debug("[ sgi_ip22_imc: unimplemented read from " |
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"address 0x%x, data=0x%08x ]\n", |
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(int)relative_addr, (int)odata); |
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} |
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} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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/* |
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* dev_sgi_ip22_unknown_access(): |
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* |
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* A so far unknown device, used by the IP22 prom during startup. |
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*/ |
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DEVICE_ACCESS(sgi_ip22_unknown) |
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dpavlin |
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{ |
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struct sgi_ip22_data *d = extra; |
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dpavlin |
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uint64_t idata = 0, odata = 0; |
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idata = memory_readmax64(cpu, data, len); |
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switch (relative_addr) { |
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case 0x04: |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_unknown: write to address 0x%x," |
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" data=0x%08x ]\n", (int)relative_addr, (int)idata); |
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} else { |
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odata = d->unknown_timer; |
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d->unknown_timer += 100; |
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debug("[ sgi_ip22_unknown: read from address 0x%x, " |
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"data=0x%08x ]\n", (int)relative_addr, (int)odata); |
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} |
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break; |
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default: |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_unknown: unimplemented write to " |
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"address 0x%x, data=0x%08x ]\n", |
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(int)relative_addr, (int)idata); |
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} else { |
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debug("[ sgi_ip22_unknown: unimplemented read from " |
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"address 0x%x, data=0x%08x ]\n", |
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(int)relative_addr, (int)odata); |
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} |
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} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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/* |
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* dev_sgi_ip22_unknown2_access(): |
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* |
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* A so far unknown device, used by the IP22 prom during startup. |
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*/ |
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dpavlin |
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DEVICE_ACCESS(sgi_ip22_unknown2) |
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dpavlin |
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{ |
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dpavlin |
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struct sgi_ip22_data *d = extra; |
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dpavlin |
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uint64_t idata = 0, odata = 0; |
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int regnr; |
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idata = memory_readmax64(cpu, data, len); |
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regnr = relative_addr / sizeof(uint32_t); |
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if (writeflag == MEM_WRITE) |
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d->unknown2_reg[regnr] = idata; |
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else |
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odata = d->unknown2_reg[regnr]; |
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switch (relative_addr) { |
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default: |
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if (writeflag == MEM_WRITE) { |
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debug("[ sgi_ip22_unknown2: unimplemented write " |
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"to address 0x%x, data=0x%08x ]\n", |
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(int)relative_addr, (int)idata); |
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} else { |
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debug("[ sgi_ip22_unknown2: unimplemented read from " |
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"address 0x%x, data=0x%08x ]\n", |
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(int)relative_addr, (int)odata); |
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} |
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} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
239 |
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return 1; |
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} |
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dpavlin |
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DEVICE_ACCESS(sgi_ip22_sysid) |
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dpavlin |
4 |
{ |
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dpavlin |
42 |
struct sgi_ip22_data *d = extra; |
247 |
dpavlin |
4 |
uint64_t idata = 0, odata = 0; |
248 |
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249 |
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idata = memory_readmax64(cpu, data, len); |
250 |
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251 |
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if (writeflag == MEM_WRITE) { |
252 |
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debug("[ sgi_ip22_sysid: write to address 0x%x, " |
253 |
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"data=0x%08x ]\n", (int)relative_addr, (int)idata); |
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} else { |
255 |
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/* |
256 |
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* According to NetBSD's sgimips/ip22.c: |
257 |
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* |
258 |
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* printf("IOC rev %d, machine %s, board rev %d\n", |
259 |
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* (sysid >> 5) & 0x07, |
260 |
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* (sysid & 1) ? "Indigo2 (Fullhouse)" : "Indy (Guiness)", |
261 |
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* (sysid >> 1) & 0x0f); |
262 |
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*/ |
263 |
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264 |
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/* IOC rev 1, Guiness, board rev 3: */ |
265 |
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odata = (1 << 5) + (3 << 1) + (d->guiness_flag? 0 : 1); |
266 |
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267 |
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debug("[ sgi_ip22_sysid: read from address 0x%x, data=" |
268 |
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"0x%08x ]\n", (int)relative_addr, (int)odata); |
269 |
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} |
270 |
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271 |
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if (writeflag == MEM_READ) |
272 |
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memory_writemax64(cpu, data, len, odata); |
273 |
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274 |
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return 1; |
275 |
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} |
276 |
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277 |
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278 |
dpavlin |
22 |
DEVICE_ACCESS(sgi_ip22) |
279 |
dpavlin |
4 |
{ |
280 |
dpavlin |
42 |
struct sgi_ip22_data *d = extra; |
281 |
dpavlin |
4 |
uint64_t idata = 0, odata = 0; |
282 |
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int regnr; |
283 |
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284 |
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idata = memory_readmax64(cpu, data, len); |
285 |
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regnr = relative_addr / sizeof(uint32_t); |
286 |
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287 |
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if (writeflag == MEM_WRITE) |
288 |
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d->reg[regnr] = idata; |
289 |
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else |
290 |
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odata = d->reg[regnr]; |
291 |
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292 |
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/* Read from/write to the sgi_ip22: */ |
293 |
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switch (relative_addr) { |
294 |
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case 0x00: /* local0 irq stat */ |
295 |
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if (writeflag == MEM_WRITE) { |
296 |
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debug("[ sgi_ip22: write to local0 IRQ STAT, " |
297 |
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"data=0x%llx ]\n", (long long)idata); |
298 |
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} else { |
299 |
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debug("[ sgi_ip22: read from local0 IRQ STAT, " |
300 |
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"data=0x%llx ]\n", (long long)odata); |
301 |
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} |
302 |
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break; |
303 |
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case 0x04: /* local0 irq mask */ |
304 |
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if (writeflag == MEM_WRITE) { |
305 |
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/* |
306 |
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* Ugly hack: if an interrupt is asserted, and someone |
307 |
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* writes to this mask register, the interrupt should |
308 |
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* be masked. That is, sgi_ip22_interrupt() in |
309 |
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* src/machine.c has to be called to deal with this. |
310 |
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* The ugly solution I choose here is to deassert |
311 |
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* some interrupt which should never be used anyway. |
312 |
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* (TODO: Fix this.) |
313 |
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*/ |
314 |
dpavlin |
34 |
|
315 |
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fatal("TODO: ip22 legacy interrupt rewrite!\n"); |
316 |
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abort(); |
317 |
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318 |
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// cpu_interrupt_ack(cpu, 8 + 63); |
319 |
dpavlin |
42 |
// debug("[ sgi_ip22: write to local0 IRQ MASK, " |
320 |
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// "data=0x%llx ]\n", (long long)idata); |
321 |
dpavlin |
4 |
} else { |
322 |
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debug("[ sgi_ip22: read from local0 IRQ MASK, " |
323 |
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"data=0x%llx ]\n", (long long)odata); |
324 |
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} |
325 |
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break; |
326 |
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case 0x08: /* local1 irq stat */ |
327 |
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if (writeflag == MEM_WRITE) { |
328 |
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debug("[ sgi_ip22: write to local1 IRQ STAT, " |
329 |
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"data=0x%llx ]\n", (long long)idata); |
330 |
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} else { |
331 |
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debug("[ sgi_ip22: read from local1 IRQ STAT, " |
332 |
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"data=0x%llx ]\n", (long long)odata); |
333 |
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} |
334 |
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break; |
335 |
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case 0x0c: /* local1 irq mask */ |
336 |
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if (writeflag == MEM_WRITE) { |
337 |
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/* See commen above, about local0 irq mask. */ |
338 |
dpavlin |
34 |
|
339 |
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fatal("TODO: ip22 legacy interrupt rewrite!\n"); |
340 |
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abort(); |
341 |
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// cpu_interrupt_ack(cpu, 8 + 63); |
342 |
dpavlin |
42 |
// debug("[ sgi_ip22: write to local1 IRQ MASK, " |
343 |
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// "data=0x%llx ]\n", (long long)idata); |
344 |
dpavlin |
4 |
} else { |
345 |
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debug("[ sgi_ip22: read from local1 IRQ MASK, " |
346 |
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"data=0x%llx ]\n", (long long)odata); |
347 |
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} |
348 |
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break; |
349 |
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case 0x10: |
350 |
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if (writeflag == MEM_WRITE) { |
351 |
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debug("[ sgi_ip22: write to mappable IRQ STAT, " |
352 |
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"data=0x%llx ]\n", (long long)idata); |
353 |
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} else { |
354 |
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debug("[ sgi_ip22: read from mappable IRQ STAT, " |
355 |
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"data=0x%llx ]\n", (long long)odata); |
356 |
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} |
357 |
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break; |
358 |
|
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case 0x14: |
359 |
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if (writeflag == MEM_WRITE) { |
360 |
|
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debug("[ sgi_ip22: write to mappable local0 IRQ " |
361 |
|
|
"MASK, data=0x%llx ]\n", (long long)idata); |
362 |
|
|
} else { |
363 |
|
|
debug("[ sgi_ip22: read from mappable local0 IRQ " |
364 |
|
|
"MASK, data=0x%llx ]\n", (long long)odata); |
365 |
|
|
} |
366 |
|
|
break; |
367 |
|
|
case 0x18: |
368 |
|
|
if (writeflag == MEM_WRITE) { |
369 |
|
|
debug("[ sgi_ip22: write to mappable local1 IRQ " |
370 |
|
|
"MASK, data=0x%llx ]\n", (long long)idata); |
371 |
|
|
} else { |
372 |
|
|
debug("[ sgi_ip22: read from mappable local1 IRQ " |
373 |
|
|
"MASK, data=0x%llx ]\n", (long long)odata); |
374 |
|
|
} |
375 |
|
|
break; |
376 |
|
|
case 0x38: /* timer count */ |
377 |
|
|
if (writeflag == MEM_WRITE) { |
378 |
|
|
/* Two byte values are written to this address, |
379 |
|
|
sequentially... TODO */ |
380 |
|
|
} else { |
381 |
|
|
/* The timer is decreased by the tick function. */ |
382 |
|
|
} |
383 |
|
|
break; |
384 |
|
|
case 0x3b: /* ? */ |
385 |
|
|
odata = random(); |
386 |
|
|
break; |
387 |
|
|
case 0x3c: /* timer control */ |
388 |
|
|
break; |
389 |
|
|
case 0x3f: /* ? */ |
390 |
|
|
odata = random(); |
391 |
|
|
break; |
392 |
|
|
default: |
393 |
|
|
if (writeflag == MEM_WRITE) { |
394 |
|
|
debug("[ sgi_ip22: unimplemented write to address " |
395 |
|
|
"0x%x, data=0x%02x ]\n", (int)relative_addr, |
396 |
|
|
(int)idata); |
397 |
|
|
} else { |
398 |
|
|
debug("[ sgi_ip22: unimplemented read from address " |
399 |
|
|
"0x%llx ]\n", (long long)relative_addr); |
400 |
|
|
} |
401 |
|
|
} |
402 |
|
|
|
403 |
|
|
if (writeflag == MEM_READ) |
404 |
|
|
memory_writemax64(cpu, data, len, odata); |
405 |
|
|
|
406 |
|
|
return 1; |
407 |
|
|
} |
408 |
|
|
|
409 |
|
|
|
410 |
|
|
struct sgi_ip22_data *dev_sgi_ip22_init(struct machine *machine, |
411 |
|
|
struct memory *mem, uint64_t baseaddr, int guiness_flag) |
412 |
|
|
{ |
413 |
dpavlin |
42 |
struct sgi_ip22_data *d; |
414 |
|
|
|
415 |
|
|
CHECK_ALLOCATION(d = malloc(sizeof(struct sgi_ip22_data))); |
416 |
dpavlin |
4 |
memset(d, 0, sizeof(struct sgi_ip22_data)); |
417 |
dpavlin |
42 |
|
418 |
dpavlin |
4 |
d->guiness_flag = guiness_flag; |
419 |
|
|
|
420 |
|
|
memory_device_register(mem, "sgi_ip22", baseaddr, DEV_SGI_IP22_LENGTH, |
421 |
dpavlin |
20 |
dev_sgi_ip22_access, (void *)d, DM_DEFAULT, NULL); |
422 |
dpavlin |
4 |
memory_device_register(mem, "sgi_ip22_sysid", 0x1fbd9858, 0x8, |
423 |
dpavlin |
20 |
dev_sgi_ip22_sysid_access, (void *)d, DM_DEFAULT, NULL); |
424 |
dpavlin |
4 |
memory_device_register(mem, "sgi_ip22_imc", IP22_IMC_BASE, |
425 |
|
|
DEV_SGI_IP22_IMC_LENGTH, dev_sgi_ip22_imc_access, (void *)d, |
426 |
dpavlin |
20 |
DM_DEFAULT, NULL); |
427 |
dpavlin |
4 |
memory_device_register(mem, "sgi_ip22_unknown", 0x1fa01000, 0x10, |
428 |
dpavlin |
20 |
dev_sgi_ip22_unknown_access, (void *)d, DM_DEFAULT, NULL); |
429 |
dpavlin |
4 |
memory_device_register(mem, "sgi_ip22_unknown2", IP22_UNKNOWN2_BASE, |
430 |
|
|
DEV_SGI_IP22_UNKNOWN2_LENGTH, dev_sgi_ip22_unknown2_access, |
431 |
dpavlin |
20 |
(void *)d, DM_DEFAULT, NULL); |
432 |
dpavlin |
4 |
|
433 |
|
|
machine_add_tickfunction(machine, dev_sgi_ip22_tick, d, |
434 |
dpavlin |
42 |
SGI_IP22_TICK_SHIFT); |
435 |
dpavlin |
4 |
|
436 |
|
|
return d; |
437 |
|
|
} |
438 |
|
|
|