/[gxemul]/trunk/src/devices/dev_sgi_ip22.c
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Annotation of /trunk/src/devices/dev_sgi_ip22.c

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Revision 22 - (hide annotations)
Mon Oct 8 16:19:37 2007 UTC (16 years, 7 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 dpavlin 4 /*
2 dpavlin 22 * Copyright (C) 2004-2006 Anders Gavare. All rights reserved.
3 dpavlin 4 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 22 * $Id: dev_sgi_ip22.c,v 1.27 2006/01/01 13:17:17 debug Exp $
29 dpavlin 4 *
30     * SGI IP22 stuff.
31     */
32    
33     #include <stdio.h>
34     #include <stdlib.h>
35     #include <string.h>
36    
37     #include "cpu.h"
38     #include "devices.h"
39     #include "machine.h"
40     #include "memory.h"
41     #include "misc.h"
42    
43     #include "imcreg.h"
44    
45    
46     #define SGI_IP22_TICK_SHIFT 14
47    
48    
49     /*
50     * dev_sgi_ip22_tick():
51     */
52     void dev_sgi_ip22_tick(struct cpu *cpu, void *extra)
53     {
54     struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
55    
56     if (d->reg[0x38 / 4] != 0)
57     d->reg[0x38 / 4] --;
58     }
59    
60    
61     /*
62     * dev_sgi_ip22_imc_access():
63     *
64     * The memory controller (?).
65     */
66 dpavlin 22 DEVICE_ACCESS(sgi_ip22_imc)
67 dpavlin 4 {
68     struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
69     uint64_t idata = 0, odata = 0;
70     int regnr;
71    
72 dpavlin 18 if (writeflag == MEM_WRITE)
73     idata = memory_readmax64(cpu, data, len);
74    
75 dpavlin 4 regnr = relative_addr / sizeof(uint32_t);
76    
77     if (writeflag == MEM_WRITE)
78     d->imc_reg[regnr] = idata;
79     else
80     odata = d->imc_reg[regnr];
81    
82     switch (relative_addr) {
83     case (IMC_CPUCTRL0 - IP22_IMC_BASE):
84     if (writeflag == MEM_WRITE) {
85     /* debug("[ sgi_ip22_imc: write to "
86     "IMC_CPUCTRL0, data=0x%08x ]\n", (int)idata); */
87     } else {
88     /* debug("[ sgi_ip22_imc: read from IMC_CPUCTRL0, "
89     "data=0x%08x ]\n", (int)odata); */
90     }
91     break;
92     case (IMC_SYSID - IP22_IMC_BASE):
93     if (writeflag == MEM_WRITE) {
94     debug("[ sgi_ip22_imc: unimplemented write "
95     "IMC_SYSID, data=0x%08x ]\n", (int)idata);
96     } else {
97     /* Lowest 4 bits are the revision bits. */
98     odata = 3; /* + IMC_SYSID_HAVEISA; */
99     /* debug("[ sgi_ip22_imc: read from IMC_SYSID, "
100     "data=0x%08x ]\n", (int)odata); */
101     }
102     break;
103     case (IMC_WDOG - IP22_IMC_BASE):
104     if (writeflag == MEM_WRITE) {
105     /* debug("[ sgi_ip22_imc: write to IMC_WDOG, "
106     "data=0x%08x ]\n", (int)idata); */
107     } else {
108     /* debug("[ sgi_ip22_imc: read from IMC_WDOG, "
109     "data=0x%08x ]\n", (int)odata); */
110     }
111     break;
112     case (IMC_MEMCFG0 - IP22_IMC_BASE):
113     if (writeflag == MEM_WRITE) {
114     debug("[ sgi_ip22_imc: unimplemented write "
115     "IMC_MEMCFG0, data=0x%08x ]\n", (int)idata);
116     } else {
117     odata = 0x3100 + (0x8000000 >> 22); /* ? TODO */
118     /* debug("[ sgi_ip22_imc: read from IMC_MEMCFG0,"
119     " data=0x%08x ]\n", (int)odata); */
120     }
121     break;
122     case (IMC_MEMCFG1 - IP22_IMC_BASE):
123     if (writeflag == MEM_WRITE) {
124     debug("[ sgi_ip22_imc: unimplemented write "
125     "IMC_MEMCFG1, data=0x%08x ]\n", (int)idata);
126     } else {
127     odata = 0;
128     /* debug("[ sgi_ip22_imc: read from IMC_MEMCFG1, "
129     "data=0x%08x ]\n", (int)odata); */
130     }
131     break;
132     case (IMC_EEPROM - IP22_IMC_BASE):
133     /*
134     * The IP22 prom tries to access this during bootup,
135     * but I have no idea how it works.
136     */
137     if (writeflag == MEM_WRITE) {
138     debug("[ sgi_ip22_imc: write to IMC_EEPROM, data="
139     "0x%08x ]\n", (int)idata);
140     } else {
141     odata = random() & 0x1e;
142     debug("[ sgi_ip22_imc: read from IMC_WDOG, "
143     "data=0x%08x ]\n", (int)odata);
144     }
145     break;
146     default:
147     if (writeflag == MEM_WRITE) {
148     debug("[ sgi_ip22_imc: unimplemented write to "
149     "address 0x%x, data=0x%08x ]\n",
150     (int)relative_addr, (int)idata);
151     } else {
152     debug("[ sgi_ip22_imc: unimplemented read from "
153     "address 0x%x, data=0x%08x ]\n",
154     (int)relative_addr, (int)odata);
155     }
156     }
157    
158     if (writeflag == MEM_READ)
159     memory_writemax64(cpu, data, len, odata);
160    
161     return 1;
162     }
163    
164    
165     /*
166     * dev_sgi_ip22_unknown_access():
167     *
168     * A so far unknown device, used by the IP22 prom during startup.
169     */
170 dpavlin 22 DEVICE_ACCESS(sgi_ip22_unknown)
171 dpavlin 4 {
172     struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
173     uint64_t idata = 0, odata = 0;
174    
175     idata = memory_readmax64(cpu, data, len);
176    
177     switch (relative_addr) {
178     case 0x04:
179     if (writeflag == MEM_WRITE) {
180     debug("[ sgi_ip22_unknown: write to address 0x%x,"
181     " data=0x%08x ]\n", (int)relative_addr, (int)idata);
182     } else {
183     odata = d->unknown_timer;
184     d->unknown_timer += 100;
185     debug("[ sgi_ip22_unknown: read from address 0x%x, "
186     "data=0x%08x ]\n", (int)relative_addr, (int)odata);
187     }
188     break;
189     default:
190     if (writeflag == MEM_WRITE) {
191     debug("[ sgi_ip22_unknown: unimplemented write to "
192     "address 0x%x, data=0x%08x ]\n",
193     (int)relative_addr, (int)idata);
194     } else {
195     debug("[ sgi_ip22_unknown: unimplemented read from "
196     "address 0x%x, data=0x%08x ]\n",
197     (int)relative_addr, (int)odata);
198     }
199     }
200    
201     if (writeflag == MEM_READ)
202     memory_writemax64(cpu, data, len, odata);
203    
204     return 1;
205     }
206    
207    
208     /*
209     * dev_sgi_ip22_unknown2_access():
210     *
211     * A so far unknown device, used by the IP22 prom during startup.
212     */
213 dpavlin 22 DEVICE_ACCESS(sgi_ip22_unknown2)
214 dpavlin 4 {
215     struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
216     uint64_t idata = 0, odata = 0;
217     int regnr;
218    
219     idata = memory_readmax64(cpu, data, len);
220     regnr = relative_addr / sizeof(uint32_t);
221    
222     if (writeflag == MEM_WRITE)
223     d->unknown2_reg[regnr] = idata;
224     else
225     odata = d->unknown2_reg[regnr];
226    
227     switch (relative_addr) {
228     default:
229     if (writeflag == MEM_WRITE) {
230     debug("[ sgi_ip22_unknown2: unimplemented write "
231     "to address 0x%x, data=0x%08x ]\n",
232     (int)relative_addr, (int)idata);
233     } else {
234     debug("[ sgi_ip22_unknown2: unimplemented read from "
235     "address 0x%x, data=0x%08x ]\n",
236     (int)relative_addr, (int)odata);
237     }
238     }
239    
240     if (writeflag == MEM_READ)
241     memory_writemax64(cpu, data, len, odata);
242    
243     return 1;
244     }
245    
246    
247     /*
248     * dev_sgi_ip22_sysid_access():
249     */
250 dpavlin 22 DEVICE_ACCESS(sgi_ip22_sysid)
251 dpavlin 4 {
252     struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
253     uint64_t idata = 0, odata = 0;
254    
255     idata = memory_readmax64(cpu, data, len);
256    
257     if (writeflag == MEM_WRITE) {
258     debug("[ sgi_ip22_sysid: write to address 0x%x, "
259     "data=0x%08x ]\n", (int)relative_addr, (int)idata);
260     } else {
261     /*
262     * According to NetBSD's sgimips/ip22.c:
263     *
264     * printf("IOC rev %d, machine %s, board rev %d\n",
265     * (sysid >> 5) & 0x07,
266     * (sysid & 1) ? "Indigo2 (Fullhouse)" : "Indy (Guiness)",
267     * (sysid >> 1) & 0x0f);
268     */
269    
270     /* IOC rev 1, Guiness, board rev 3: */
271     odata = (1 << 5) + (3 << 1) + (d->guiness_flag? 0 : 1);
272    
273     debug("[ sgi_ip22_sysid: read from address 0x%x, data="
274     "0x%08x ]\n", (int)relative_addr, (int)odata);
275     }
276    
277     if (writeflag == MEM_READ)
278     memory_writemax64(cpu, data, len, odata);
279    
280     return 1;
281     }
282    
283    
284     /*
285     * dev_sgi_ip22_access():
286     */
287 dpavlin 22 DEVICE_ACCESS(sgi_ip22)
288 dpavlin 4 {
289     struct sgi_ip22_data *d = (struct sgi_ip22_data *) extra;
290     uint64_t idata = 0, odata = 0;
291     int regnr;
292    
293     idata = memory_readmax64(cpu, data, len);
294     regnr = relative_addr / sizeof(uint32_t);
295    
296     if (writeflag == MEM_WRITE)
297     d->reg[regnr] = idata;
298     else
299     odata = d->reg[regnr];
300    
301     /* Read from/write to the sgi_ip22: */
302     switch (relative_addr) {
303     case 0x00: /* local0 irq stat */
304     if (writeflag == MEM_WRITE) {
305     debug("[ sgi_ip22: write to local0 IRQ STAT, "
306     "data=0x%llx ]\n", (long long)idata);
307     } else {
308     debug("[ sgi_ip22: read from local0 IRQ STAT, "
309     "data=0x%llx ]\n", (long long)odata);
310     }
311     break;
312     case 0x04: /* local0 irq mask */
313     if (writeflag == MEM_WRITE) {
314     /*
315     * Ugly hack: if an interrupt is asserted, and someone
316     * writes to this mask register, the interrupt should
317     * be masked. That is, sgi_ip22_interrupt() in
318     * src/machine.c has to be called to deal with this.
319     * The ugly solution I choose here is to deassert
320     * some interrupt which should never be used anyway.
321     * (TODO: Fix this.)
322     */
323     cpu_interrupt_ack(cpu, 8 + 63);
324     debug("[ sgi_ip22: write to local0 IRQ MASK, "
325     "data=0x%llx ]\n", (long long)idata);
326     } else {
327     debug("[ sgi_ip22: read from local0 IRQ MASK, "
328     "data=0x%llx ]\n", (long long)odata);
329     }
330     break;
331     case 0x08: /* local1 irq stat */
332     if (writeflag == MEM_WRITE) {
333     debug("[ sgi_ip22: write to local1 IRQ STAT, "
334     "data=0x%llx ]\n", (long long)idata);
335     } else {
336     debug("[ sgi_ip22: read from local1 IRQ STAT, "
337     "data=0x%llx ]\n", (long long)odata);
338     }
339     break;
340     case 0x0c: /* local1 irq mask */
341     if (writeflag == MEM_WRITE) {
342     /* See commen above, about local0 irq mask. */
343     cpu_interrupt_ack(cpu, 8 + 63);
344     debug("[ sgi_ip22: write to local1 IRQ MASK, "
345     "data=0x%llx ]\n", (long long)idata);
346     } else {
347     debug("[ sgi_ip22: read from local1 IRQ MASK, "
348     "data=0x%llx ]\n", (long long)odata);
349     }
350     break;
351     case 0x10:
352     if (writeflag == MEM_WRITE) {
353     debug("[ sgi_ip22: write to mappable IRQ STAT, "
354     "data=0x%llx ]\n", (long long)idata);
355     } else {
356     debug("[ sgi_ip22: read from mappable IRQ STAT, "
357     "data=0x%llx ]\n", (long long)odata);
358     }
359     break;
360     case 0x14:
361     if (writeflag == MEM_WRITE) {
362     debug("[ sgi_ip22: write to mappable local0 IRQ "
363     "MASK, data=0x%llx ]\n", (long long)idata);
364     } else {
365     debug("[ sgi_ip22: read from mappable local0 IRQ "
366     "MASK, data=0x%llx ]\n", (long long)odata);
367     }
368     break;
369     case 0x18:
370     if (writeflag == MEM_WRITE) {
371     debug("[ sgi_ip22: write to mappable local1 IRQ "
372     "MASK, data=0x%llx ]\n", (long long)idata);
373     } else {
374     debug("[ sgi_ip22: read from mappable local1 IRQ "
375     "MASK, data=0x%llx ]\n", (long long)odata);
376     }
377     break;
378     case 0x38: /* timer count */
379     if (writeflag == MEM_WRITE) {
380     /* Two byte values are written to this address,
381     sequentially... TODO */
382     } else {
383     /* The timer is decreased by the tick function. */
384     }
385     break;
386     case 0x3b: /* ? */
387     odata = random();
388     break;
389     case 0x3c: /* timer control */
390     break;
391     case 0x3f: /* ? */
392     odata = random();
393     break;
394     default:
395     if (writeflag == MEM_WRITE) {
396     debug("[ sgi_ip22: unimplemented write to address "
397     "0x%x, data=0x%02x ]\n", (int)relative_addr,
398     (int)idata);
399     } else {
400     debug("[ sgi_ip22: unimplemented read from address "
401     "0x%llx ]\n", (long long)relative_addr);
402     }
403     }
404    
405     if (writeflag == MEM_READ)
406     memory_writemax64(cpu, data, len, odata);
407    
408     return 1;
409     }
410    
411    
412     /*
413     * dev_sgi_ip22_init():
414     */
415     struct sgi_ip22_data *dev_sgi_ip22_init(struct machine *machine,
416     struct memory *mem, uint64_t baseaddr, int guiness_flag)
417     {
418     struct sgi_ip22_data *d = malloc(sizeof(struct sgi_ip22_data));
419     if (d == NULL) {
420     fprintf(stderr, "out of memory\n");
421     exit(1);
422     }
423     memset(d, 0, sizeof(struct sgi_ip22_data));
424     d->guiness_flag = guiness_flag;
425    
426     memory_device_register(mem, "sgi_ip22", baseaddr, DEV_SGI_IP22_LENGTH,
427 dpavlin 20 dev_sgi_ip22_access, (void *)d, DM_DEFAULT, NULL);
428 dpavlin 4 memory_device_register(mem, "sgi_ip22_sysid", 0x1fbd9858, 0x8,
429 dpavlin 20 dev_sgi_ip22_sysid_access, (void *)d, DM_DEFAULT, NULL);
430 dpavlin 4 memory_device_register(mem, "sgi_ip22_imc", IP22_IMC_BASE,
431     DEV_SGI_IP22_IMC_LENGTH, dev_sgi_ip22_imc_access, (void *)d,
432 dpavlin 20 DM_DEFAULT, NULL);
433 dpavlin 4 memory_device_register(mem, "sgi_ip22_unknown", 0x1fa01000, 0x10,
434 dpavlin 20 dev_sgi_ip22_unknown_access, (void *)d, DM_DEFAULT, NULL);
435 dpavlin 4 memory_device_register(mem, "sgi_ip22_unknown2", IP22_UNKNOWN2_BASE,
436     DEV_SGI_IP22_UNKNOWN2_LENGTH, dev_sgi_ip22_unknown2_access,
437 dpavlin 20 (void *)d, DM_DEFAULT, NULL);
438 dpavlin 4
439     machine_add_tickfunction(machine, dev_sgi_ip22_tick, d,
440     SGI_IP22_TICK_SHIFT);
441    
442     return d;
443     }
444    

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