/[gxemul]/trunk/src/devices/dev_scc.c
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Contents of /trunk/src/devices/dev_scc.c

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Revision 18 - (show annotations)
Mon Oct 8 16:19:11 2007 UTC (12 years, 7 months ago) by dpavlin
File MIME type: text/plain
File size: 13212 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1004 2005/10/27 14:01:10 debug Exp $
20051011        Passing -A as the default boot arg for CATS (works fine with
                OpenBSD/cats).
20051012	Fixing the VGA cursor offset bug, and speeding up framebuffer
		redraws if character cells contain the same thing as during
		the last redraw.
20051013	Adding a slow strd ARM instruction hack.
20051017	Minor updates: Adding a dummy i80321 Verde controller (for
		XScale emulation), fixing the disassembly of the ARM "ldrd"
		instruction, adding "support" for less-than-4KB pages for ARM
		(by not adding them to translation tables).
20051020	Continuing on some HPCarm stuff. A NetBSD/hpcarm kernel prints
		some boot messages on an emulated Jornada 720.
		Making dev_ram work better with dyntrans (speeds up some things
		quite a bit).
20051021	Automatically generating some of the most common ARM load/store
		multiple instructions.
20051022	Better statistics gathering for the ARM load/store multiple.
		Various other dyntrans and device updates.
20051023	Various minor updates.
20051024	Continuing; minor device and dyntrans fine-tuning. Adding the
		first "reasonable" instruction combination hacks for ARM (the
		cores of NetBSD/cats' memset and memcpy).
20051025	Fixing a dyntrans-related bug in dev_vga. Also changing the
		dyntrans low/high access notification to only be updated on
		writes, not reads. Hopefully it will be enough. (dev_vga in
		charcell mode now seems to work correctly with both reads and
		writes.)
		Experimenting with gathering dyntrans statistics (which parts
		of emulated RAM that are actually executed), and adding
		instruction combination hacks for cache cleaning and a part of
		NetBSD's scanc() function.
20051026	Adding a bitmap for ARM emulation which indicates if a page is
		(specifically) user accessible; loads and stores with the t-
		flag set can now use the translation arrays, which results in
		a measurable speedup.
20051027	Dyntrans updates; adding an extra bitmap array for 32-bit
		emulation modes, speeding up the check whether a physical page
		has any code translations or not (O(n) -> O(1)). Doing a
		similar reduction of O(n) to O(1) by avoiding the scan through
		the translation entries on a translation update (32-bit mode
		only).
		Various other minor hacks.
20051029	Quick release, without any testing at all.

==============  RELEASE 0.3.6.2  ==============


1 /*
2 * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_scc.c,v 1.28 2005/10/26 14:37:04 debug Exp $
29 *
30 * Serial controller on some DECsystems and SGI machines. (Z8530 ?)
31 * Most of the code in here is written for DECsystem emulation, though.
32 *
33 * NOTE:
34 * Each scc device is responsible for two lines; the first scc device
35 * controls mouse (0) and keyboard (1), and the second device controls
36 * serial ports (2 and 3).
37 *
38 * TODO:
39 * Mouse support!!! (scc0 and scc1 need to cooperate, in order to
40 * emulate the same lk201 behaviour as when using the dc device)
41 * DMA
42 * More correct interrupt support.
43 */
44
45 #include <stdio.h>
46 #include <stdlib.h>
47 #include <string.h>
48
49 #include "console.h"
50 #include "cpu.h"
51 #include "devices.h"
52 #include "machine.h"
53 #include "memory.h"
54 #include "misc.h"
55
56 #include "sccreg.h"
57
58
59 #define SCC_TICK_SHIFT 14
60
61 #define N_SCC_PORTS 2
62 #define N_SCC_REGS 16
63 #define MAX_QUEUE_LEN 1024
64
65 /* #define SCC_DEBUG */
66
67
68 struct scc_data {
69 int irq_nr;
70 int use_fb;
71 int console_handle;
72
73 int scc_nr;
74 int addrmul;
75
76 int register_select_in_progress[N_SCC_PORTS];
77 int register_selected[N_SCC_PORTS];
78
79 unsigned char scc_register_r[N_SCC_PORTS * N_SCC_REGS];
80 unsigned char scc_register_w[N_SCC_PORTS * N_SCC_REGS];
81
82 unsigned char rx_queue_char[N_SCC_PORTS * MAX_QUEUE_LEN];
83 int cur_rx_queue_pos_write[N_SCC_PORTS];
84 int cur_rx_queue_pos_read[N_SCC_PORTS];
85
86 struct lk201_data lk201;
87 };
88
89
90 /*
91 * dev_scc_add_to_rx_queue():
92 *
93 * Add a character to the receive queue.
94 */
95 void dev_scc_add_to_rx_queue(void *e, int ch, int portnr)
96 {
97 struct scc_data *d = (struct scc_data *) e;
98 int scc_nr;
99
100 /* DC's keyboard port ==> SCC keyboard port */
101 if (portnr == 0)
102 portnr = 3;
103
104 scc_nr = portnr / N_SCC_PORTS;
105 if (scc_nr != d->scc_nr)
106 return;
107
108 portnr &= (N_SCC_PORTS - 1);
109
110 d->rx_queue_char[portnr * MAX_QUEUE_LEN +
111 d->cur_rx_queue_pos_write[portnr]] = ch;
112 d->cur_rx_queue_pos_write[portnr] ++;
113 if (d->cur_rx_queue_pos_write[portnr] == MAX_QUEUE_LEN)
114 d->cur_rx_queue_pos_write[portnr] = 0;
115
116 if (d->cur_rx_queue_pos_write[portnr] ==
117 d->cur_rx_queue_pos_read[portnr])
118 fatal("warning: add_to_rx_queue(): rx_queue overrun!\n");
119 }
120
121
122 static int rx_avail(struct scc_data *d, int portnr)
123 {
124 return d->cur_rx_queue_pos_write[portnr] !=
125 d->cur_rx_queue_pos_read[portnr];
126 }
127
128
129 static unsigned char rx_nextchar(struct scc_data *d, int portnr)
130 {
131 unsigned char ch;
132 ch = d->rx_queue_char[portnr * MAX_QUEUE_LEN +
133 d->cur_rx_queue_pos_read[portnr]];
134 d->cur_rx_queue_pos_read[portnr]++;
135 if (d->cur_rx_queue_pos_read[portnr] == MAX_QUEUE_LEN)
136 d->cur_rx_queue_pos_read[portnr] = 0;
137 return ch;
138 }
139
140
141 /*
142 * dev_scc_tick():
143 */
144 void dev_scc_tick(struct cpu *cpu, void *extra)
145 {
146 int i;
147 struct scc_data *d = (struct scc_data *) extra;
148
149 /* Add keystrokes to the rx queue: */
150 if (d->use_fb == 0 && d->scc_nr == 1) {
151 if (console_charavail(d->console_handle))
152 dev_scc_add_to_rx_queue(extra, console_readchar(
153 d->console_handle), 2);
154 }
155 if (d->use_fb == 1 && d->scc_nr == 1)
156 lk201_tick(&d->lk201);
157
158 for (i=0; i<N_SCC_PORTS; i++) {
159 d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |= SCC_RR0_TX_EMPTY;
160 d->scc_register_r[i * N_SCC_REGS + SCC_RR1] = 0;
161 /* No receive errors */
162
163 d->scc_register_r[i * N_SCC_REGS + SCC_RR0] &=
164 ~SCC_RR0_RX_AVAIL;
165 if (rx_avail(d, i))
166 d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |=
167 SCC_RR0_RX_AVAIL;
168
169 /*
170 * Interrupts:
171 * (NOTE: Interrupt enables are always at channel A)
172 */
173 if (d->scc_register_w[N_SCC_REGS + SCC_WR9] &
174 SCC_WR9_MASTER_IE) {
175 /* TX interrupts? */
176 if (d->scc_register_w[i * N_SCC_REGS + SCC_WR1] &
177 SCC_WR1_TX_IE) {
178 if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
179 & SCC_RR3_TX_IP_A ||
180 d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
181 & SCC_RR3_TX_IP_B)
182 cpu_interrupt(cpu, d->irq_nr);
183 }
184
185 /* RX interrupts? */
186 if (d->scc_register_w[N_SCC_REGS + SCC_WR1] &
187 (SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_RXI_ALL_CHAR)) {
188 if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0]
189 & SCC_RR0_RX_AVAIL) {
190 if (i == SCC_CHANNEL_A)
191 d->scc_register_r[N_SCC_REGS +
192 SCC_RR3] |= SCC_RR3_RX_IP_A;
193 else
194 d->scc_register_r[N_SCC_REGS +
195 SCC_RR3] |= SCC_RR3_RX_IP_B;
196 }
197
198 if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
199 & SCC_RR3_RX_IP_A ||
200 d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
201 & SCC_RR3_RX_IP_B)
202 cpu_interrupt(cpu, d->irq_nr);
203 }
204
205 if (d->scc_register_w[N_SCC_REGS + SCC_WR1] &
206 SCC_WR1_DMA_MODE) {
207 if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0]
208 & SCC_RR0_RX_AVAIL) {
209 if (i == SCC_CHANNEL_A)
210 d->scc_register_r[N_SCC_REGS +
211 SCC_RR3] |=
212 SCC_RR3_EXT_IP_A;
213 else
214 d->scc_register_r[N_SCC_REGS +
215 SCC_RR3] |=
216 SCC_RR3_EXT_IP_B;
217 }
218
219 if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
220 & SCC_RR3_EXT_IP_A ||
221 d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
222 & SCC_RR3_EXT_IP_B)
223 {
224 cpu_interrupt(cpu, d->irq_nr);
225 /* TODO: huh? */
226 cpu_interrupt(cpu, 8 + 0x02000000);
227 }
228 }
229 }
230 }
231 }
232
233
234 /*
235 * dev_scc_dma_func():
236 */
237 int dev_scc_dma_func(struct cpu *cpu, void *extra, uint64_t addr,
238 size_t dma_len, int tx)
239 {
240 /* printf("dev_scc_dma_func(): addr = %08x, len = %i\n",
241 (int)addr, (int)dma_len); */
242 unsigned char word[4];
243 struct scc_data *d = (struct scc_data *) extra;
244 int n;
245
246 int port = SCC_CHANNEL_A; /* TODO */
247
248 if (tx) {
249 do {
250 cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
251 sizeof(word), MEM_READ, NO_EXCEPTIONS | PHYSICAL);
252
253 lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, word[1]);
254 /* Loopback: */
255 if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14]
256 & SCC_WR14_LOCAL_LOOPB)
257 dev_scc_add_to_rx_queue(d, word[1],
258 d->scc_nr * 2 + port);
259
260 addr += sizeof(word);
261 } while ((addr & 0xffc) != 0);
262
263 dev_scc_tick(cpu, extra);
264 return 1;
265 } else {
266 printf("dev_scc_dma_func(): addr = %08x, len = %i\n",
267 (int)addr, (int)dma_len);
268
269
270 /* TODO: all this is just nonsense */
271
272 n = 0;
273 while (rx_avail(d, port)) {
274 word[0] = word[1] = word[2] = word[3] = 0;
275 word[0] = word[1] = word[2] = word[3] =
276 rx_nextchar(d, port);
277 n++;
278 cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
279 sizeof(word), MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
280
281 addr += sizeof(word);
282 /* Half-page? */
283 if ((addr & 0x7fc) == 0)
284 break;
285 }
286 dev_scc_tick(cpu, extra);
287 return n*4;
288 }
289 }
290
291
292 /*
293 * dev_scc_access():
294 */
295 int dev_scc_access(struct cpu *cpu, struct memory *mem,
296 uint64_t relative_addr, unsigned char *data, size_t len,
297 int writeflag, void *extra)
298 {
299 struct scc_data *d = (struct scc_data *) extra;
300 uint64_t idata = 0, odata = 0;
301 int port;
302 int ultrix_mode = 0;
303
304 if (writeflag == MEM_WRITE)
305 idata = memory_readmax64(cpu, data, len);
306
307 /* relative_addr /= d->addrmul; */
308 /* See SGI comment below instead. */
309 /*
310 * SGI writes command to 0x0f, and data to 0x1f.
311 * (TODO: This works for port nr 0, how about port nr 1?)
312 */
313 if ((relative_addr & 0x0f) == 0xf) {
314 if (relative_addr == 0x0f)
315 relative_addr = 1;
316 else
317 relative_addr = 5;
318 }
319
320 port = relative_addr / 8;
321 relative_addr &= 7;
322
323 dev_scc_tick(cpu, extra);
324
325 /*
326 * Ultrix writes words such as 0x1200 to relative address 0,
327 * instead of writing the byte 0x12 directly to address 1.
328 */
329 if ((relative_addr == 0 || relative_addr == 4) && (idata & 0xff) == 0) {
330 ultrix_mode = 1;
331 relative_addr ++;
332 idata >>= 8;
333 }
334
335 switch (relative_addr) {
336 case 1: /* command */
337 if (writeflag==MEM_READ) {
338 odata = d->scc_register_r[port * N_SCC_REGS +
339 d->register_selected[port]];
340
341 if (d->register_selected[port] == SCC_RR3) {
342 if (port == SCC_CHANNEL_B)
343 fatal("WARNING! scc channel B has "
344 "no RR3\n");
345
346 d->scc_register_r[port * N_SCC_REGS +
347 SCC_RR3] = 0;
348 cpu_interrupt_ack(cpu, d->irq_nr);
349 }
350
351 #ifdef SCC_DEBUG
352 fatal("[ scc: port %i, register %i, read value "
353 "0x%02x ]\n", port, d->register_selected[port],
354 (int)odata);
355 #endif
356 d->register_select_in_progress[port] = 0;
357 d->register_selected[port] = 0;
358 /* debug("[ scc: (port %i) read from 0x%08lx ]\n",
359 port, (long)relative_addr); */
360 } else {
361 /* If no register is selected, then select one.
362 Otherwise, write to the selected register. */
363 if (d->register_select_in_progress[port] == 0) {
364 d->register_select_in_progress[port] = 1;
365 d->register_selected[port] = idata;
366 d->register_selected[port] &= (N_SCC_REGS-1);
367 } else {
368 d->scc_register_w[port * N_SCC_REGS +
369 d->register_selected[port]] = idata;
370 #ifdef SCC_DEBUG
371 fatal("[ scc: port %i, register %i, write "
372 "value 0x%02x ]\n", port,
373 d->register_selected[port], idata);
374 #endif
375
376 d->scc_register_r[port * N_SCC_REGS +
377 SCC_RR12] = d->scc_register_w[port *
378 N_SCC_REGS + SCC_WR12];
379 d->scc_register_r[port * N_SCC_REGS +
380 SCC_RR13] = d->scc_register_w[port *
381 N_SCC_REGS + SCC_WR13];
382
383 d->register_select_in_progress[port] = 0;
384 d->register_selected[port] = 0;
385 }
386 }
387 break;
388 case 5: /* data */
389 if (writeflag==MEM_READ) {
390 if (rx_avail(d, port))
391 odata = rx_nextchar(d, port);
392
393 /* TODO: perhaps only clear the RX part of RR3? */
394 d->scc_register_r[N_SCC_REGS + SCC_RR3] = 0;
395 cpu_interrupt_ack(cpu, d->irq_nr);
396
397 debug("[ scc: (port %i) read from 0x%08lx: 0x%02x ]\n",
398 port, (long)relative_addr, (int)odata);
399 } else {
400 /* debug("[ scc: (port %i) write to 0x%08lx: "
401 "0x%08x ]\n", port, (long)relative_addr,
402 (int)idata); */
403
404 /* Send the character: */
405 lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, idata);
406
407 /* Loopback: */
408 if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14]
409 & SCC_WR14_LOCAL_LOOPB)
410 dev_scc_add_to_rx_queue(d, idata, d->scc_nr
411 * 2 + port);
412
413 /* TX interrupt: */
414 if (d->scc_register_w[port * N_SCC_REGS + SCC_WR9] &
415 SCC_WR9_MASTER_IE &&
416 d->scc_register_w[port * N_SCC_REGS + SCC_WR1] &
417 SCC_WR1_TX_IE) {
418 if (port == SCC_CHANNEL_A)
419 d->scc_register_r[N_SCC_REGS + SCC_RR3]
420 |= SCC_RR3_TX_IP_A;
421 else
422 d->scc_register_r[N_SCC_REGS + SCC_RR3]
423 |= SCC_RR3_TX_IP_B;
424 }
425
426 dev_scc_tick(cpu, extra);
427 }
428 break;
429 default:
430 if (writeflag==MEM_READ) {
431 debug("[ scc: (port %i) read from 0x%08lx ]\n",
432 port, (long)relative_addr);
433 } else {
434 debug("[ scc: (port %i) write to 0x%08lx: 0x%08x ]\n",
435 port, (long)relative_addr, (int)idata);
436 }
437 }
438
439 if (ultrix_mode && writeflag == MEM_READ) {
440 odata <<= 8;
441 }
442
443 if (writeflag == MEM_READ)
444 memory_writemax64(cpu, data, len, odata);
445
446 return 1;
447 }
448
449
450 /*
451 * dev_scc_init():
452 *
453 * use_fb = non-zero when using graphical console + keyboard
454 * scc_nr = 0 or 1
455 * addmul = 1 in most cases, 8 on SGI?
456 */
457 void *dev_scc_init(struct machine *machine, struct memory *mem,
458 uint64_t baseaddr, int irq_nr, int use_fb, int scc_nr, int addrmul)
459 {
460 struct scc_data *d;
461
462 d = malloc(sizeof(struct scc_data));
463 if (d == NULL) {
464 fprintf(stderr, "out of memory\n");
465 exit(1);
466 }
467 memset(d, 0, sizeof(struct scc_data));
468 d->irq_nr = irq_nr;
469 d->scc_nr = scc_nr;
470 d->use_fb = use_fb;
471 d->addrmul = addrmul;
472 d->console_handle = console_start_slave(machine, "SCC");
473
474 lk201_init(&d->lk201, use_fb, dev_scc_add_to_rx_queue,
475 d->console_handle, d);
476
477 memory_device_register(mem, "scc", baseaddr, DEV_SCC_LENGTH,
478 dev_scc_access, d, MEM_DEFAULT, NULL);
479 machine_add_tickfunction(machine, dev_scc_tick, d, SCC_TICK_SHIFT);
480
481 return (void *) d;
482 }
483

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