/[gxemul]/trunk/src/devices/dev_scc.c
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Contents of /trunk/src/devices/dev_scc.c

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Revision 42 - (show annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 13512 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============


1 /*
2 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_scc.c,v 1.40 2007/06/15 19:57:34 debug Exp $
29 *
30 * COMMENT: Serial controller used in some DECsystem and SGI machines
31 *
32 * Hm... Same as Z8530? Most of the code in here is written for DECsystem
33 * emulation, though.
34 *
35 * NOTE:
36 * Each scc device is responsible for two lines; the first scc device
37 * controls mouse (0) and keyboard (1), and the second device controls
38 * serial ports (2 and 3).
39 *
40 * TODO:
41 * Mouse support!!! (scc0 and scc1 need to cooperate, in order to
42 * emulate the same lk201 behaviour as when using the dc device)
43 * DMA
44 * More correct interrupt support.
45 *
46 ******************************************************************************
47 * _____ ___ ____ ___ _
48 * |_ _/ _ \| _ \ / _ \| |
49 * | || | | | | | | | | | |
50 * | || |_| | |_| | |_| |_|
51 * |_| \___/|____/ \___/(_)
52 *
53 * Since this is actually a Z8530, it should be merged with dev_z8530.c!
54 */
55
56 #include <stdio.h>
57 #include <stdlib.h>
58 #include <string.h>
59
60 #include "console.h"
61 #include "cpu.h"
62 #include "devices.h"
63 #include "machine.h"
64 #include "memory.h"
65 #include "misc.h"
66
67 #include "sccreg.h"
68
69
70 #define SCC_TICK_SHIFT 14
71
72 #define N_SCC_PORTS 2
73 #define N_SCC_REGS 16
74 #define MAX_QUEUE_LEN 1024
75
76 /* #define SCC_DEBUG */
77
78
79 struct scc_data {
80 int irq_nr;
81 int use_fb;
82 int console_handle;
83
84 int scc_nr;
85 int addrmul;
86
87 int register_select_in_progress[N_SCC_PORTS];
88 int register_selected[N_SCC_PORTS];
89
90 unsigned char scc_register_r[N_SCC_PORTS * N_SCC_REGS];
91 unsigned char scc_register_w[N_SCC_PORTS * N_SCC_REGS];
92
93 unsigned char rx_queue_char[N_SCC_PORTS * MAX_QUEUE_LEN];
94 int cur_rx_queue_pos_write[N_SCC_PORTS];
95 int cur_rx_queue_pos_read[N_SCC_PORTS];
96
97 struct lk201_data lk201;
98 };
99
100
101 /*
102 * dev_scc_add_to_rx_queue():
103 *
104 * Add a character to the receive queue.
105 */
106 void dev_scc_add_to_rx_queue(void *e, int ch, int portnr)
107 {
108 struct scc_data *d = (struct scc_data *) e;
109 int scc_nr;
110
111 /* DC's keyboard port ==> SCC keyboard port */
112 if (portnr == 0)
113 portnr = 3;
114
115 scc_nr = portnr / N_SCC_PORTS;
116 if (scc_nr != d->scc_nr)
117 return;
118
119 portnr &= (N_SCC_PORTS - 1);
120
121 d->rx_queue_char[portnr * MAX_QUEUE_LEN +
122 d->cur_rx_queue_pos_write[portnr]] = ch;
123 d->cur_rx_queue_pos_write[portnr] ++;
124 if (d->cur_rx_queue_pos_write[portnr] == MAX_QUEUE_LEN)
125 d->cur_rx_queue_pos_write[portnr] = 0;
126
127 if (d->cur_rx_queue_pos_write[portnr] ==
128 d->cur_rx_queue_pos_read[portnr])
129 fatal("warning: add_to_rx_queue(): rx_queue overrun!\n");
130 }
131
132
133 static int rx_avail(struct scc_data *d, int portnr)
134 {
135 return d->cur_rx_queue_pos_write[portnr] !=
136 d->cur_rx_queue_pos_read[portnr];
137 }
138
139
140 static unsigned char rx_nextchar(struct scc_data *d, int portnr)
141 {
142 unsigned char ch;
143 ch = d->rx_queue_char[portnr * MAX_QUEUE_LEN +
144 d->cur_rx_queue_pos_read[portnr]];
145 d->cur_rx_queue_pos_read[portnr]++;
146 if (d->cur_rx_queue_pos_read[portnr] == MAX_QUEUE_LEN)
147 d->cur_rx_queue_pos_read[portnr] = 0;
148 return ch;
149 }
150
151
152 DEVICE_TICK(scc)
153 {
154 struct scc_data *d = extra;
155 int i;
156
157 /* Add keystrokes to the rx queue: */
158 if (d->use_fb == 0 && d->scc_nr == 1) {
159 if (console_charavail(d->console_handle))
160 dev_scc_add_to_rx_queue(extra, console_readchar(
161 d->console_handle), 2);
162 }
163 if (d->use_fb == 1 && d->scc_nr == 1)
164 lk201_tick(cpu->machine, &d->lk201);
165
166 for (i=0; i<N_SCC_PORTS; i++) {
167 d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |= SCC_RR0_TX_EMPTY;
168 d->scc_register_r[i * N_SCC_REGS + SCC_RR1] = 0;
169 /* No receive errors */
170
171 d->scc_register_r[i * N_SCC_REGS + SCC_RR0] &=
172 ~SCC_RR0_RX_AVAIL;
173 if (rx_avail(d, i))
174 d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |=
175 SCC_RR0_RX_AVAIL;
176
177 /*
178 * Interrupts:
179 * (NOTE: Interrupt enables are always at channel A)
180 */
181 if (d->scc_register_w[N_SCC_REGS + SCC_WR9] &
182 SCC_WR9_MASTER_IE) {
183 /* TX interrupts? */
184 if (d->scc_register_w[i * N_SCC_REGS + SCC_WR1] &
185 SCC_WR1_TX_IE) {
186 if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
187 & SCC_RR3_TX_IP_A ||
188 d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
189 & SCC_RR3_TX_IP_B) {
190 fatal("TODO: legacy rewrite!\n");
191 abort();
192 // cpu_interrupt(cpu, d->irq_nr);
193 }
194 }
195
196 /* RX interrupts? */
197 if (d->scc_register_w[N_SCC_REGS + SCC_WR1] &
198 (SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_RXI_ALL_CHAR)) {
199 if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0]
200 & SCC_RR0_RX_AVAIL) {
201 if (i == SCC_CHANNEL_A)
202 d->scc_register_r[N_SCC_REGS +
203 SCC_RR3] |= SCC_RR3_RX_IP_A;
204 else
205 d->scc_register_r[N_SCC_REGS +
206 SCC_RR3] |= SCC_RR3_RX_IP_B;
207 }
208
209 if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
210 & SCC_RR3_RX_IP_A ||
211 d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
212 & SCC_RR3_RX_IP_B) {
213 fatal("TODO: legacy rewrite!\n");
214 abort();
215 // cpu_interrupt(cpu, d->irq_nr);
216 }
217 }
218
219 if (d->scc_register_w[N_SCC_REGS + SCC_WR1] &
220 SCC_WR1_DMA_MODE) {
221 if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0]
222 & SCC_RR0_RX_AVAIL) {
223 if (i == SCC_CHANNEL_A)
224 d->scc_register_r[N_SCC_REGS +
225 SCC_RR3] |=
226 SCC_RR3_EXT_IP_A;
227 else
228 d->scc_register_r[N_SCC_REGS +
229 SCC_RR3] |=
230 SCC_RR3_EXT_IP_B;
231 }
232
233 if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
234 & SCC_RR3_EXT_IP_A ||
235 d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
236 & SCC_RR3_EXT_IP_B)
237 {
238 fatal("TODO: legacy rewrite!\n");
239 abort();
240 // cpu_interrupt(cpu, d->irq_nr);
241 /* TODO: huh? */
242 //cpu_interrupt(cpu, 8 + 0x02000000);
243 }
244 }
245 }
246 }
247 }
248
249
250 /*
251 * dev_scc_dma_func():
252 */
253 int dev_scc_dma_func(struct cpu *cpu, void *extra, uint64_t addr,
254 size_t dma_len, int tx)
255 {
256 /* printf("dev_scc_dma_func(): addr = %08x, len = %i\n",
257 (int)addr, (int)dma_len); */
258 unsigned char word[4];
259 struct scc_data *d = (struct scc_data *) extra;
260 int n;
261
262 int port = SCC_CHANNEL_A; /* TODO */
263
264 if (tx) {
265 do {
266 cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
267 sizeof(word), MEM_READ, NO_EXCEPTIONS | PHYSICAL);
268
269 lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, word[1]);
270 /* Loopback: */
271 if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14]
272 & SCC_WR14_LOCAL_LOOPB)
273 dev_scc_add_to_rx_queue(d, word[1],
274 d->scc_nr * 2 + port);
275
276 addr += sizeof(word);
277 } while ((addr & 0xffc) != 0);
278
279 dev_scc_tick(cpu, extra);
280 return 1;
281 } else {
282 printf("dev_scc_dma_func(): addr = %08x, len = %i\n",
283 (int)addr, (int)dma_len);
284
285
286 /* TODO: all this is just nonsense */
287
288 n = 0;
289 while (rx_avail(d, port)) {
290 word[0] = word[1] = word[2] = word[3] = 0;
291 word[0] = word[1] = word[2] = word[3] =
292 rx_nextchar(d, port);
293 n++;
294 cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
295 sizeof(word), MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
296
297 addr += sizeof(word);
298 /* Half-page? */
299 if ((addr & 0x7fc) == 0)
300 break;
301 }
302 dev_scc_tick(cpu, extra);
303 return n*4;
304 }
305 }
306
307
308 DEVICE_ACCESS(scc)
309 {
310 struct scc_data *d = extra;
311 uint64_t idata = 0, odata = 0;
312 int port;
313 int ultrix_mode = 0;
314
315 if (writeflag == MEM_WRITE)
316 idata = memory_readmax64(cpu, data, len);
317
318 /* relative_addr /= d->addrmul; */
319 /* See SGI comment below instead. */
320 /*
321 * SGI writes command to 0x0f, and data to 0x1f.
322 * (TODO: This works for port nr 0, how about port nr 1?)
323 */
324 if ((relative_addr & 0x0f) == 0xf) {
325 if (relative_addr == 0x0f)
326 relative_addr = 1;
327 else
328 relative_addr = 5;
329 }
330
331 port = relative_addr / 8;
332 relative_addr &= 7;
333
334 dev_scc_tick(cpu, extra);
335
336 /*
337 * Ultrix writes words such as 0x1200 to relative address 0,
338 * instead of writing the byte 0x12 directly to address 1.
339 */
340 if ((relative_addr == 0 || relative_addr == 4) && (idata & 0xff) == 0) {
341 ultrix_mode = 1;
342 relative_addr ++;
343 idata >>= 8;
344 }
345
346 switch (relative_addr) {
347 case 1: /* command */
348 if (writeflag==MEM_READ) {
349 odata = d->scc_register_r[port * N_SCC_REGS +
350 d->register_selected[port]];
351
352 if (d->register_selected[port] == SCC_RR3) {
353 if (port == SCC_CHANNEL_B)
354 fatal("WARNING! scc channel B has "
355 "no RR3\n");
356
357 d->scc_register_r[port * N_SCC_REGS +
358 SCC_RR3] = 0;
359
360 fatal("TODO: legacy rewrite!\n");
361 abort();
362 // cpu_interrupt_ack(cpu, d->irq_nr);
363 }
364
365 #ifdef SCC_DEBUG
366 fatal("[ scc: port %i, register %i, read value "
367 "0x%02x ]\n", port, d->register_selected[port],
368 (int)odata);
369 #endif
370 d->register_select_in_progress[port] = 0;
371 d->register_selected[port] = 0;
372 /* debug("[ scc: (port %i) read from 0x%08lx ]\n",
373 port, (long)relative_addr); */
374 } else {
375 /* If no register is selected, then select one.
376 Otherwise, write to the selected register. */
377 if (d->register_select_in_progress[port] == 0) {
378 d->register_select_in_progress[port] = 1;
379 d->register_selected[port] = idata;
380 d->register_selected[port] &= (N_SCC_REGS-1);
381 } else {
382 d->scc_register_w[port * N_SCC_REGS +
383 d->register_selected[port]] = idata;
384 #ifdef SCC_DEBUG
385 fatal("[ scc: port %i, register %i, write "
386 "value 0x%02x ]\n", port,
387 d->register_selected[port], idata);
388 #endif
389
390 d->scc_register_r[port * N_SCC_REGS +
391 SCC_RR12] = d->scc_register_w[port *
392 N_SCC_REGS + SCC_WR12];
393 d->scc_register_r[port * N_SCC_REGS +
394 SCC_RR13] = d->scc_register_w[port *
395 N_SCC_REGS + SCC_WR13];
396
397 d->register_select_in_progress[port] = 0;
398 d->register_selected[port] = 0;
399 }
400 }
401 break;
402 case 5: /* data */
403 if (writeflag==MEM_READ) {
404 if (rx_avail(d, port))
405 odata = rx_nextchar(d, port);
406
407 /* TODO: perhaps only clear the RX part of RR3? */
408 d->scc_register_r[N_SCC_REGS + SCC_RR3] = 0;
409
410 fatal("TODO: legacy rewrite!\n");
411 abort();
412 // cpu_interrupt_ack(cpu, d->irq_nr);
413
414 // debug("[ scc: (port %i) read from 0x%08lx: 0x%02x ]\n",
415 // port, (long)relative_addr, (int)odata);
416 } else {
417 /* debug("[ scc: (port %i) write to 0x%08lx: "
418 "0x%08x ]\n", port, (long)relative_addr,
419 (int)idata); */
420
421 /* Send the character: */
422 lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, idata);
423
424 /* Loopback: */
425 if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14]
426 & SCC_WR14_LOCAL_LOOPB)
427 dev_scc_add_to_rx_queue(d, idata, d->scc_nr
428 * 2 + port);
429
430 /* TX interrupt: */
431 if (d->scc_register_w[port * N_SCC_REGS + SCC_WR9] &
432 SCC_WR9_MASTER_IE &&
433 d->scc_register_w[port * N_SCC_REGS + SCC_WR1] &
434 SCC_WR1_TX_IE) {
435 if (port == SCC_CHANNEL_A)
436 d->scc_register_r[N_SCC_REGS + SCC_RR3]
437 |= SCC_RR3_TX_IP_A;
438 else
439 d->scc_register_r[N_SCC_REGS + SCC_RR3]
440 |= SCC_RR3_TX_IP_B;
441 }
442
443 dev_scc_tick(cpu, extra);
444 }
445 break;
446 default:
447 if (writeflag==MEM_READ) {
448 debug("[ scc: (port %i) read from 0x%08lx ]\n",
449 port, (long)relative_addr);
450 } else {
451 debug("[ scc: (port %i) write to 0x%08lx: 0x%08x ]\n",
452 port, (long)relative_addr, (int)idata);
453 }
454 }
455
456 if (ultrix_mode && writeflag == MEM_READ) {
457 odata <<= 8;
458 }
459
460 if (writeflag == MEM_READ)
461 memory_writemax64(cpu, data, len, odata);
462
463 return 1;
464 }
465
466
467 /*
468 * dev_scc_init():
469 *
470 * use_fb = non-zero when using graphical console + keyboard
471 * scc_nr = 0 or 1
472 * addmul = 1 in most cases, 8 on SGI?
473 */
474 void *dev_scc_init(struct machine *machine, struct memory *mem,
475 uint64_t baseaddr, int irq_nr, int use_fb, int scc_nr, int addrmul)
476 {
477 struct scc_data *d;
478
479 CHECK_ALLOCATION(d = malloc(sizeof(struct scc_data)));
480 memset(d, 0, sizeof(struct scc_data));
481
482 d->irq_nr = irq_nr;
483 d->scc_nr = scc_nr;
484 d->use_fb = use_fb;
485 d->addrmul = addrmul;
486 d->console_handle = console_start_slave(machine, "SCC", 1);
487
488 lk201_init(&d->lk201, use_fb, dev_scc_add_to_rx_queue,
489 d->console_handle, d);
490
491 memory_device_register(mem, "scc", baseaddr, DEV_SCC_LENGTH,
492 dev_scc_access, d, DM_DEFAULT, NULL);
493 machine_add_tickfunction(machine, dev_scc_tick, d, SCC_TICK_SHIFT);
494
495 return (void *) d;
496 }
497

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