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/* |
/* |
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* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_scc.c,v 1.33 2006/03/04 12:38:48 debug Exp $ |
* $Id: dev_scc.c,v 1.37 2007/01/28 14:15:30 debug Exp $ |
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* |
* |
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* Serial controller on some DECsystems and SGI machines. (Z8530 ?) |
* Serial controller on some DECsystems and SGI machines. (Z8530 ?) |
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* Most of the code in here is written for DECsystem emulation, though. |
* Most of the code in here is written for DECsystem emulation, though. |
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} |
} |
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/* |
DEVICE_TICK(scc) |
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* dev_scc_tick(): |
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*/ |
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void dev_scc_tick(struct cpu *cpu, void *extra) |
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{ |
{ |
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int i; |
int i; |
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struct scc_data *d = (struct scc_data *) extra; |
struct scc_data *d = (struct scc_data *) extra; |
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d->console_handle), 2); |
d->console_handle), 2); |
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} |
} |
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if (d->use_fb == 1 && d->scc_nr == 1) |
if (d->use_fb == 1 && d->scc_nr == 1) |
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lk201_tick(&d->lk201); |
lk201_tick(cpu->machine, &d->lk201); |
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for (i=0; i<N_SCC_PORTS; i++) { |
for (i=0; i<N_SCC_PORTS; i++) { |
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d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |= SCC_RR0_TX_EMPTY; |
d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |= SCC_RR0_TX_EMPTY; |
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if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
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& SCC_RR3_TX_IP_A || |
& SCC_RR3_TX_IP_A || |
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d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
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& SCC_RR3_TX_IP_B) |
& SCC_RR3_TX_IP_B) { |
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cpu_interrupt(cpu, d->irq_nr); |
fatal("TODO: legacy rewrite!\n"); |
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abort(); |
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// cpu_interrupt(cpu, d->irq_nr); |
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} |
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} |
} |
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/* RX interrupts? */ |
/* RX interrupts? */ |
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if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
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& SCC_RR3_RX_IP_A || |
& SCC_RR3_RX_IP_A || |
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d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
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& SCC_RR3_RX_IP_B) |
& SCC_RR3_RX_IP_B) { |
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cpu_interrupt(cpu, d->irq_nr); |
fatal("TODO: legacy rewrite!\n"); |
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abort(); |
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// cpu_interrupt(cpu, d->irq_nr); |
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} |
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} |
} |
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if (d->scc_register_w[N_SCC_REGS + SCC_WR1] & |
if (d->scc_register_w[N_SCC_REGS + SCC_WR1] & |
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d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
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& SCC_RR3_EXT_IP_B) |
& SCC_RR3_EXT_IP_B) |
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{ |
{ |
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cpu_interrupt(cpu, d->irq_nr); |
fatal("TODO: legacy rewrite!\n"); |
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abort(); |
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// cpu_interrupt(cpu, d->irq_nr); |
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/* TODO: huh? */ |
/* TODO: huh? */ |
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cpu_interrupt(cpu, 8 + 0x02000000); |
//cpu_interrupt(cpu, 8 + 0x02000000); |
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} |
} |
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} |
} |
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} |
} |
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} |
} |
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/* |
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* dev_scc_access(): |
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*/ |
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DEVICE_ACCESS(scc) |
DEVICE_ACCESS(scc) |
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{ |
{ |
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struct scc_data *d = (struct scc_data *) extra; |
struct scc_data *d = (struct scc_data *) extra; |
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d->scc_register_r[port * N_SCC_REGS + |
d->scc_register_r[port * N_SCC_REGS + |
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SCC_RR3] = 0; |
SCC_RR3] = 0; |
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cpu_interrupt_ack(cpu, d->irq_nr); |
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fatal("TODO: legacy rewrite!\n"); |
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abort(); |
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// cpu_interrupt_ack(cpu, d->irq_nr); |
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} |
} |
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#ifdef SCC_DEBUG |
#ifdef SCC_DEBUG |
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/* TODO: perhaps only clear the RX part of RR3? */ |
/* TODO: perhaps only clear the RX part of RR3? */ |
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d->scc_register_r[N_SCC_REGS + SCC_RR3] = 0; |
d->scc_register_r[N_SCC_REGS + SCC_RR3] = 0; |
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cpu_interrupt_ack(cpu, d->irq_nr); |
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fatal("TODO: legacy rewrite!\n"); |
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abort(); |
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// cpu_interrupt_ack(cpu, d->irq_nr); |
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debug("[ scc: (port %i) read from 0x%08lx: 0x%02x ]\n", |
debug("[ scc: (port %i) read from 0x%08lx: 0x%02x ]\n", |
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port, (long)relative_addr, (int)odata); |
port, (long)relative_addr, (int)odata); |