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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_scc.c,v 1.27 2005/02/25 06:14:30 debug Exp $ |
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* |
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* Serial controller on some DECsystems and SGI machines. (Z8530 ?) |
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* Most of the code in here is written for DECsystem emulation, though. |
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* |
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* NOTE: |
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* Each scc device is responsible for two lines; the first scc device |
| 35 |
* controls mouse (0) and keyboard (1), and the second device controls |
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* serial ports (2 and 3). |
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* |
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* TODO: |
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* Mouse support!!! (scc0 and scc1 need to cooperate, in order to |
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* emulate the same lk201 behaviour as when using the dc device) |
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* DMA |
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* More correct interrupt support. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "console.h" |
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#include "cpu.h" |
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#include "devices.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "sccreg.h" |
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|
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|
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#define SCC_TICK_SHIFT 14 |
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|
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#define N_SCC_PORTS 2 |
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#define N_SCC_REGS 16 |
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#define MAX_QUEUE_LEN 1024 |
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|
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/* #define SCC_DEBUG */ |
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|
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|
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struct scc_data { |
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int irq_nr; |
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int use_fb; |
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int console_handle; |
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|
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int scc_nr; |
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int addrmul; |
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|
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int register_select_in_progress[N_SCC_PORTS]; |
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int register_selected[N_SCC_PORTS]; |
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|
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unsigned char scc_register_r[N_SCC_PORTS * N_SCC_REGS]; |
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unsigned char scc_register_w[N_SCC_PORTS * N_SCC_REGS]; |
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|
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unsigned char rx_queue_char[N_SCC_PORTS * MAX_QUEUE_LEN]; |
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int cur_rx_queue_pos_write[N_SCC_PORTS]; |
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int cur_rx_queue_pos_read[N_SCC_PORTS]; |
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|
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struct lk201_data lk201; |
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}; |
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|
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|
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/* |
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* dev_scc_add_to_rx_queue(): |
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* |
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* Add a character to the receive queue. |
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*/ |
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void dev_scc_add_to_rx_queue(void *e, int ch, int portnr) |
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{ |
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struct scc_data *d = (struct scc_data *) e; |
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int scc_nr; |
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|
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/* DC's keyboard port ==> SCC keyboard port */ |
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if (portnr == 0) |
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portnr = 3; |
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|
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scc_nr = portnr / N_SCC_PORTS; |
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if (scc_nr != d->scc_nr) |
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return; |
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|
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portnr &= (N_SCC_PORTS - 1); |
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|
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d->rx_queue_char[portnr * MAX_QUEUE_LEN + |
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d->cur_rx_queue_pos_write[portnr]] = ch; |
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d->cur_rx_queue_pos_write[portnr] ++; |
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if (d->cur_rx_queue_pos_write[portnr] == MAX_QUEUE_LEN) |
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d->cur_rx_queue_pos_write[portnr] = 0; |
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|
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if (d->cur_rx_queue_pos_write[portnr] == |
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d->cur_rx_queue_pos_read[portnr]) |
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fatal("warning: add_to_rx_queue(): rx_queue overrun!\n"); |
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} |
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|
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|
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static int rx_avail(struct scc_data *d, int portnr) |
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{ |
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return d->cur_rx_queue_pos_write[portnr] != |
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d->cur_rx_queue_pos_read[portnr]; |
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} |
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|
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|
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static unsigned char rx_nextchar(struct scc_data *d, int portnr) |
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{ |
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unsigned char ch; |
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ch = d->rx_queue_char[portnr * MAX_QUEUE_LEN + |
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d->cur_rx_queue_pos_read[portnr]]; |
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d->cur_rx_queue_pos_read[portnr]++; |
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if (d->cur_rx_queue_pos_read[portnr] == MAX_QUEUE_LEN) |
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d->cur_rx_queue_pos_read[portnr] = 0; |
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return ch; |
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} |
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|
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|
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/* |
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* dev_scc_tick(): |
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*/ |
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void dev_scc_tick(struct cpu *cpu, void *extra) |
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{ |
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int i; |
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struct scc_data *d = (struct scc_data *) extra; |
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|
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/* Add keystrokes to the rx queue: */ |
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if (d->use_fb == 0 && d->scc_nr == 1) { |
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if (console_charavail(d->console_handle)) |
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dev_scc_add_to_rx_queue(extra, console_readchar( |
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d->console_handle), 2); |
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} |
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if (d->use_fb == 1 && d->scc_nr == 1) |
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lk201_tick(&d->lk201); |
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|
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for (i=0; i<N_SCC_PORTS; i++) { |
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d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |= SCC_RR0_TX_EMPTY; |
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d->scc_register_r[i * N_SCC_REGS + SCC_RR1] = 0; |
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/* No receive errors */ |
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|
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d->scc_register_r[i * N_SCC_REGS + SCC_RR0] &= |
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~SCC_RR0_RX_AVAIL; |
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if (rx_avail(d, i)) |
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d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |= |
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SCC_RR0_RX_AVAIL; |
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|
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/* |
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* Interrupts: |
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* (NOTE: Interrupt enables are always at channel A) |
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*/ |
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if (d->scc_register_w[N_SCC_REGS + SCC_WR9] & |
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SCC_WR9_MASTER_IE) { |
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/* TX interrupts? */ |
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if (d->scc_register_w[i * N_SCC_REGS + SCC_WR1] & |
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SCC_WR1_TX_IE) { |
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if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
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& SCC_RR3_TX_IP_A || |
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d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
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& SCC_RR3_TX_IP_B) |
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cpu_interrupt(cpu, d->irq_nr); |
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} |
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|
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/* RX interrupts? */ |
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if (d->scc_register_w[N_SCC_REGS + SCC_WR1] & |
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(SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_RXI_ALL_CHAR)) { |
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if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |
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& SCC_RR0_RX_AVAIL) { |
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if (i == SCC_CHANNEL_A) |
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d->scc_register_r[N_SCC_REGS + |
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SCC_RR3] |= SCC_RR3_RX_IP_A; |
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else |
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d->scc_register_r[N_SCC_REGS + |
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SCC_RR3] |= SCC_RR3_RX_IP_B; |
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} |
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|
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if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
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& SCC_RR3_RX_IP_A || |
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d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
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& SCC_RR3_RX_IP_B) |
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cpu_interrupt(cpu, d->irq_nr); |
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} |
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|
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if (d->scc_register_w[N_SCC_REGS + SCC_WR1] & |
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SCC_WR1_DMA_MODE) { |
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if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |
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& SCC_RR0_RX_AVAIL) { |
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if (i == SCC_CHANNEL_A) |
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d->scc_register_r[N_SCC_REGS + |
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SCC_RR3] |= |
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SCC_RR3_EXT_IP_A; |
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else |
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d->scc_register_r[N_SCC_REGS + |
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SCC_RR3] |= |
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SCC_RR3_EXT_IP_B; |
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} |
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|
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if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
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& SCC_RR3_EXT_IP_A || |
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d->scc_register_r[i * N_SCC_REGS + SCC_RR3] |
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& SCC_RR3_EXT_IP_B) |
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{ |
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cpu_interrupt(cpu, d->irq_nr); |
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/* TODO: huh? */ |
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cpu_interrupt(cpu, 8 + 0x02000000); |
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} |
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} |
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} |
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} |
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} |
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|
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|
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/* |
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* dev_scc_dma_func(): |
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*/ |
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int dev_scc_dma_func(struct cpu *cpu, void *extra, uint64_t addr, |
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size_t dma_len, int tx) |
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{ |
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/* printf("dev_scc_dma_func(): addr = %08x, len = %i\n", |
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(int)addr, (int)dma_len); */ |
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unsigned char word[4]; |
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struct scc_data *d = (struct scc_data *) extra; |
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int n; |
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|
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int port = SCC_CHANNEL_A; /* TODO */ |
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|
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if (tx) { |
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do { |
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cpu->memory_rw(cpu, cpu->mem, addr, &word[0], |
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sizeof(word), MEM_READ, NO_EXCEPTIONS | PHYSICAL); |
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|
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lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, word[1]); |
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/* Loopback: */ |
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if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14] |
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& SCC_WR14_LOCAL_LOOPB) |
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dev_scc_add_to_rx_queue(d, word[1], |
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d->scc_nr * 2 + port); |
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|
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addr += sizeof(word); |
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} while ((addr & 0xffc) != 0); |
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|
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dev_scc_tick(cpu, extra); |
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return 1; |
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} else { |
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printf("dev_scc_dma_func(): addr = %08x, len = %i\n", |
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(int)addr, (int)dma_len); |
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|
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|
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/* TODO: all this is just nonsense */ |
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|
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n = 0; |
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while (rx_avail(d, port)) { |
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word[0] = word[1] = word[2] = word[3] = 0; |
| 275 |
word[0] = word[1] = word[2] = word[3] = |
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rx_nextchar(d, port); |
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n++; |
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cpu->memory_rw(cpu, cpu->mem, addr, &word[0], |
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sizeof(word), MEM_WRITE, NO_EXCEPTIONS | PHYSICAL); |
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|
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addr += sizeof(word); |
| 282 |
/* Half-page? */ |
| 283 |
if ((addr & 0x7fc) == 0) |
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break; |
| 285 |
} |
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dev_scc_tick(cpu, extra); |
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return n*4; |
| 288 |
} |
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} |
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|
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|
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/* |
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* dev_scc_access(): |
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*/ |
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int dev_scc_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct scc_data *d = (struct scc_data *) extra; |
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uint64_t idata = 0, odata = 0; |
| 301 |
int port; |
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int ultrix_mode = 0; |
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|
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idata = memory_readmax64(cpu, data, len); |
| 305 |
|
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/* relative_addr /= d->addrmul; */ |
| 307 |
/* See SGI comment below instead. */ |
| 308 |
/* |
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* SGI writes command to 0x0f, and data to 0x1f. |
| 310 |
* (TODO: This works for port nr 0, how about port nr 1?) |
| 311 |
*/ |
| 312 |
if ((relative_addr & 0x0f) == 0xf) { |
| 313 |
if (relative_addr == 0x0f) |
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relative_addr = 1; |
| 315 |
else |
| 316 |
relative_addr = 5; |
| 317 |
} |
| 318 |
|
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port = relative_addr / 8; |
| 320 |
relative_addr &= 7; |
| 321 |
|
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dev_scc_tick(cpu, extra); |
| 323 |
|
| 324 |
/* |
| 325 |
* Ultrix writes words such as 0x1200 to relative address 0, |
| 326 |
* instead of writing the byte 0x12 directly to address 1. |
| 327 |
*/ |
| 328 |
if ((relative_addr == 0 || relative_addr == 4) && (idata & 0xff) == 0) { |
| 329 |
ultrix_mode = 1; |
| 330 |
relative_addr ++; |
| 331 |
idata >>= 8; |
| 332 |
} |
| 333 |
|
| 334 |
switch (relative_addr) { |
| 335 |
case 1: /* command */ |
| 336 |
if (writeflag==MEM_READ) { |
| 337 |
odata = d->scc_register_r[port * N_SCC_REGS + |
| 338 |
d->register_selected[port]]; |
| 339 |
|
| 340 |
if (d->register_selected[port] == SCC_RR3) { |
| 341 |
if (port == SCC_CHANNEL_B) |
| 342 |
fatal("WARNING! scc channel B has " |
| 343 |
"no RR3\n"); |
| 344 |
|
| 345 |
d->scc_register_r[port * N_SCC_REGS + |
| 346 |
SCC_RR3] = 0; |
| 347 |
cpu_interrupt_ack(cpu, d->irq_nr); |
| 348 |
} |
| 349 |
|
| 350 |
#ifdef SCC_DEBUG |
| 351 |
fatal("[ scc: port %i, register %i, read value " |
| 352 |
"0x%02x ]\n", port, d->register_selected[port], |
| 353 |
(int)odata); |
| 354 |
#endif |
| 355 |
d->register_select_in_progress[port] = 0; |
| 356 |
d->register_selected[port] = 0; |
| 357 |
/* debug("[ scc: (port %i) read from 0x%08lx ]\n", |
| 358 |
port, (long)relative_addr); */ |
| 359 |
} else { |
| 360 |
/* If no register is selected, then select one. |
| 361 |
Otherwise, write to the selected register. */ |
| 362 |
if (d->register_select_in_progress[port] == 0) { |
| 363 |
d->register_select_in_progress[port] = 1; |
| 364 |
d->register_selected[port] = idata; |
| 365 |
d->register_selected[port] &= (N_SCC_REGS-1); |
| 366 |
} else { |
| 367 |
d->scc_register_w[port * N_SCC_REGS + |
| 368 |
d->register_selected[port]] = idata; |
| 369 |
#ifdef SCC_DEBUG |
| 370 |
fatal("[ scc: port %i, register %i, write " |
| 371 |
"value 0x%02x ]\n", port, |
| 372 |
d->register_selected[port], idata); |
| 373 |
#endif |
| 374 |
|
| 375 |
d->scc_register_r[port * N_SCC_REGS + |
| 376 |
SCC_RR12] = d->scc_register_w[port * |
| 377 |
N_SCC_REGS + SCC_WR12]; |
| 378 |
d->scc_register_r[port * N_SCC_REGS + |
| 379 |
SCC_RR13] = d->scc_register_w[port * |
| 380 |
N_SCC_REGS + SCC_WR13]; |
| 381 |
|
| 382 |
d->register_select_in_progress[port] = 0; |
| 383 |
d->register_selected[port] = 0; |
| 384 |
} |
| 385 |
} |
| 386 |
break; |
| 387 |
case 5: /* data */ |
| 388 |
if (writeflag==MEM_READ) { |
| 389 |
if (rx_avail(d, port)) |
| 390 |
odata = rx_nextchar(d, port); |
| 391 |
|
| 392 |
/* TODO: perhaps only clear the RX part of RR3? */ |
| 393 |
d->scc_register_r[N_SCC_REGS + SCC_RR3] = 0; |
| 394 |
cpu_interrupt_ack(cpu, d->irq_nr); |
| 395 |
|
| 396 |
debug("[ scc: (port %i) read from 0x%08lx: 0x%02x ]\n", |
| 397 |
port, (long)relative_addr, (int)odata); |
| 398 |
} else { |
| 399 |
/* debug("[ scc: (port %i) write to 0x%08lx: " |
| 400 |
"0x%08x ]\n", port, (long)relative_addr, |
| 401 |
(int)idata); */ |
| 402 |
|
| 403 |
/* Send the character: */ |
| 404 |
lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, idata); |
| 405 |
|
| 406 |
/* Loopback: */ |
| 407 |
if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14] |
| 408 |
& SCC_WR14_LOCAL_LOOPB) |
| 409 |
dev_scc_add_to_rx_queue(d, idata, d->scc_nr |
| 410 |
* 2 + port); |
| 411 |
|
| 412 |
/* TX interrupt: */ |
| 413 |
if (d->scc_register_w[port * N_SCC_REGS + SCC_WR9] & |
| 414 |
SCC_WR9_MASTER_IE && |
| 415 |
d->scc_register_w[port * N_SCC_REGS + SCC_WR1] & |
| 416 |
SCC_WR1_TX_IE) { |
| 417 |
if (port == SCC_CHANNEL_A) |
| 418 |
d->scc_register_r[N_SCC_REGS + SCC_RR3] |
| 419 |
|= SCC_RR3_TX_IP_A; |
| 420 |
else |
| 421 |
d->scc_register_r[N_SCC_REGS + SCC_RR3] |
| 422 |
|= SCC_RR3_TX_IP_B; |
| 423 |
} |
| 424 |
|
| 425 |
dev_scc_tick(cpu, extra); |
| 426 |
} |
| 427 |
break; |
| 428 |
default: |
| 429 |
if (writeflag==MEM_READ) { |
| 430 |
debug("[ scc: (port %i) read from 0x%08lx ]\n", |
| 431 |
port, (long)relative_addr); |
| 432 |
} else { |
| 433 |
debug("[ scc: (port %i) write to 0x%08lx: 0x%08x ]\n", |
| 434 |
port, (long)relative_addr, (int)idata); |
| 435 |
} |
| 436 |
} |
| 437 |
|
| 438 |
if (ultrix_mode && writeflag == MEM_READ) { |
| 439 |
odata <<= 8; |
| 440 |
} |
| 441 |
|
| 442 |
if (writeflag == MEM_READ) |
| 443 |
memory_writemax64(cpu, data, len, odata); |
| 444 |
|
| 445 |
return 1; |
| 446 |
} |
| 447 |
|
| 448 |
|
| 449 |
/* |
| 450 |
* dev_scc_init(): |
| 451 |
* |
| 452 |
* use_fb = non-zero when using graphical console + keyboard |
| 453 |
* scc_nr = 0 or 1 |
| 454 |
* addmul = 1 in most cases, 8 on SGI? |
| 455 |
*/ |
| 456 |
void *dev_scc_init(struct machine *machine, struct memory *mem, |
| 457 |
uint64_t baseaddr, int irq_nr, int use_fb, int scc_nr, int addrmul) |
| 458 |
{ |
| 459 |
struct scc_data *d; |
| 460 |
|
| 461 |
d = malloc(sizeof(struct scc_data)); |
| 462 |
if (d == NULL) { |
| 463 |
fprintf(stderr, "out of memory\n"); |
| 464 |
exit(1); |
| 465 |
} |
| 466 |
memset(d, 0, sizeof(struct scc_data)); |
| 467 |
d->irq_nr = irq_nr; |
| 468 |
d->scc_nr = scc_nr; |
| 469 |
d->use_fb = use_fb; |
| 470 |
d->addrmul = addrmul; |
| 471 |
d->console_handle = console_start_slave(machine, "SCC"); |
| 472 |
|
| 473 |
lk201_init(&d->lk201, use_fb, dev_scc_add_to_rx_queue, |
| 474 |
d->console_handle, d); |
| 475 |
|
| 476 |
memory_device_register(mem, "scc", baseaddr, DEV_SCC_LENGTH, |
| 477 |
dev_scc_access, d, MEM_DEFAULT, NULL); |
| 478 |
machine_add_tickfunction(machine, dev_scc_tick, d, SCC_TICK_SHIFT); |
| 479 |
|
| 480 |
return (void *) d; |
| 481 |
} |
| 482 |
|
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