/[gxemul]/trunk/src/devices/dev_scc.c
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Annotation of /trunk/src/devices/dev_scc.c

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Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 dpavlin 4 /*
2 dpavlin 22 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3 dpavlin 4 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 22 * $Id: dev_scc.c,v 1.32 2006/01/01 13:17:17 debug Exp $
29 dpavlin 4 *
30     * Serial controller on some DECsystems and SGI machines. (Z8530 ?)
31     * Most of the code in here is written for DECsystem emulation, though.
32     *
33     * NOTE:
34     * Each scc device is responsible for two lines; the first scc device
35     * controls mouse (0) and keyboard (1), and the second device controls
36     * serial ports (2 and 3).
37     *
38     * TODO:
39     * Mouse support!!! (scc0 and scc1 need to cooperate, in order to
40     * emulate the same lk201 behaviour as when using the dc device)
41     * DMA
42     * More correct interrupt support.
43 dpavlin 22 *
44     ******************************************************************************
45     * _____ ___ ____ ___ _
46     * |_ _/ _ \| _ \ / _ \| |
47     * | || | | | | | | | | | |
48     * | || |_| | |_| | |_| |_|
49     * |_| \___/|____/ \___/(_)
50     *
51     * Since this is actually a Z8530, it should be merged with dev_z8530.c!
52 dpavlin 4 */
53    
54     #include <stdio.h>
55     #include <stdlib.h>
56     #include <string.h>
57    
58     #include "console.h"
59     #include "cpu.h"
60     #include "devices.h"
61     #include "machine.h"
62     #include "memory.h"
63     #include "misc.h"
64    
65     #include "sccreg.h"
66    
67    
68     #define SCC_TICK_SHIFT 14
69    
70     #define N_SCC_PORTS 2
71     #define N_SCC_REGS 16
72     #define MAX_QUEUE_LEN 1024
73    
74     /* #define SCC_DEBUG */
75    
76    
77     struct scc_data {
78     int irq_nr;
79     int use_fb;
80     int console_handle;
81    
82     int scc_nr;
83     int addrmul;
84    
85     int register_select_in_progress[N_SCC_PORTS];
86     int register_selected[N_SCC_PORTS];
87    
88     unsigned char scc_register_r[N_SCC_PORTS * N_SCC_REGS];
89     unsigned char scc_register_w[N_SCC_PORTS * N_SCC_REGS];
90    
91     unsigned char rx_queue_char[N_SCC_PORTS * MAX_QUEUE_LEN];
92     int cur_rx_queue_pos_write[N_SCC_PORTS];
93     int cur_rx_queue_pos_read[N_SCC_PORTS];
94    
95     struct lk201_data lk201;
96     };
97    
98    
99     /*
100     * dev_scc_add_to_rx_queue():
101     *
102     * Add a character to the receive queue.
103     */
104     void dev_scc_add_to_rx_queue(void *e, int ch, int portnr)
105     {
106     struct scc_data *d = (struct scc_data *) e;
107     int scc_nr;
108    
109     /* DC's keyboard port ==> SCC keyboard port */
110     if (portnr == 0)
111     portnr = 3;
112    
113     scc_nr = portnr / N_SCC_PORTS;
114     if (scc_nr != d->scc_nr)
115     return;
116    
117     portnr &= (N_SCC_PORTS - 1);
118    
119     d->rx_queue_char[portnr * MAX_QUEUE_LEN +
120     d->cur_rx_queue_pos_write[portnr]] = ch;
121     d->cur_rx_queue_pos_write[portnr] ++;
122     if (d->cur_rx_queue_pos_write[portnr] == MAX_QUEUE_LEN)
123     d->cur_rx_queue_pos_write[portnr] = 0;
124    
125     if (d->cur_rx_queue_pos_write[portnr] ==
126     d->cur_rx_queue_pos_read[portnr])
127     fatal("warning: add_to_rx_queue(): rx_queue overrun!\n");
128     }
129    
130    
131     static int rx_avail(struct scc_data *d, int portnr)
132     {
133     return d->cur_rx_queue_pos_write[portnr] !=
134     d->cur_rx_queue_pos_read[portnr];
135     }
136    
137    
138     static unsigned char rx_nextchar(struct scc_data *d, int portnr)
139     {
140     unsigned char ch;
141     ch = d->rx_queue_char[portnr * MAX_QUEUE_LEN +
142     d->cur_rx_queue_pos_read[portnr]];
143     d->cur_rx_queue_pos_read[portnr]++;
144     if (d->cur_rx_queue_pos_read[portnr] == MAX_QUEUE_LEN)
145     d->cur_rx_queue_pos_read[portnr] = 0;
146     return ch;
147     }
148    
149    
150     /*
151     * dev_scc_tick():
152     */
153     void dev_scc_tick(struct cpu *cpu, void *extra)
154     {
155     int i;
156     struct scc_data *d = (struct scc_data *) extra;
157    
158     /* Add keystrokes to the rx queue: */
159     if (d->use_fb == 0 && d->scc_nr == 1) {
160     if (console_charavail(d->console_handle))
161     dev_scc_add_to_rx_queue(extra, console_readchar(
162     d->console_handle), 2);
163     }
164     if (d->use_fb == 1 && d->scc_nr == 1)
165     lk201_tick(&d->lk201);
166    
167     for (i=0; i<N_SCC_PORTS; i++) {
168     d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |= SCC_RR0_TX_EMPTY;
169     d->scc_register_r[i * N_SCC_REGS + SCC_RR1] = 0;
170     /* No receive errors */
171    
172     d->scc_register_r[i * N_SCC_REGS + SCC_RR0] &=
173     ~SCC_RR0_RX_AVAIL;
174     if (rx_avail(d, i))
175     d->scc_register_r[i * N_SCC_REGS + SCC_RR0] |=
176     SCC_RR0_RX_AVAIL;
177    
178     /*
179     * Interrupts:
180     * (NOTE: Interrupt enables are always at channel A)
181     */
182     if (d->scc_register_w[N_SCC_REGS + SCC_WR9] &
183     SCC_WR9_MASTER_IE) {
184     /* TX interrupts? */
185     if (d->scc_register_w[i * N_SCC_REGS + SCC_WR1] &
186     SCC_WR1_TX_IE) {
187     if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
188     & SCC_RR3_TX_IP_A ||
189     d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
190     & SCC_RR3_TX_IP_B)
191     cpu_interrupt(cpu, d->irq_nr);
192     }
193    
194     /* RX interrupts? */
195     if (d->scc_register_w[N_SCC_REGS + SCC_WR1] &
196     (SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_RXI_ALL_CHAR)) {
197     if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0]
198     & SCC_RR0_RX_AVAIL) {
199     if (i == SCC_CHANNEL_A)
200     d->scc_register_r[N_SCC_REGS +
201     SCC_RR3] |= SCC_RR3_RX_IP_A;
202     else
203     d->scc_register_r[N_SCC_REGS +
204     SCC_RR3] |= SCC_RR3_RX_IP_B;
205     }
206    
207     if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
208     & SCC_RR3_RX_IP_A ||
209     d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
210     & SCC_RR3_RX_IP_B)
211     cpu_interrupt(cpu, d->irq_nr);
212     }
213    
214     if (d->scc_register_w[N_SCC_REGS + SCC_WR1] &
215     SCC_WR1_DMA_MODE) {
216     if (d->scc_register_r[i * N_SCC_REGS + SCC_RR0]
217     & SCC_RR0_RX_AVAIL) {
218     if (i == SCC_CHANNEL_A)
219     d->scc_register_r[N_SCC_REGS +
220     SCC_RR3] |=
221     SCC_RR3_EXT_IP_A;
222     else
223     d->scc_register_r[N_SCC_REGS +
224     SCC_RR3] |=
225     SCC_RR3_EXT_IP_B;
226     }
227    
228     if (d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
229     & SCC_RR3_EXT_IP_A ||
230     d->scc_register_r[i * N_SCC_REGS + SCC_RR3]
231     & SCC_RR3_EXT_IP_B)
232     {
233     cpu_interrupt(cpu, d->irq_nr);
234     /* TODO: huh? */
235     cpu_interrupt(cpu, 8 + 0x02000000);
236     }
237     }
238     }
239     }
240     }
241    
242    
243     /*
244     * dev_scc_dma_func():
245     */
246     int dev_scc_dma_func(struct cpu *cpu, void *extra, uint64_t addr,
247     size_t dma_len, int tx)
248     {
249     /* printf("dev_scc_dma_func(): addr = %08x, len = %i\n",
250     (int)addr, (int)dma_len); */
251     unsigned char word[4];
252     struct scc_data *d = (struct scc_data *) extra;
253     int n;
254    
255     int port = SCC_CHANNEL_A; /* TODO */
256    
257     if (tx) {
258     do {
259     cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
260     sizeof(word), MEM_READ, NO_EXCEPTIONS | PHYSICAL);
261    
262     lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, word[1]);
263     /* Loopback: */
264     if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14]
265     & SCC_WR14_LOCAL_LOOPB)
266     dev_scc_add_to_rx_queue(d, word[1],
267     d->scc_nr * 2 + port);
268    
269     addr += sizeof(word);
270     } while ((addr & 0xffc) != 0);
271    
272     dev_scc_tick(cpu, extra);
273     return 1;
274     } else {
275     printf("dev_scc_dma_func(): addr = %08x, len = %i\n",
276     (int)addr, (int)dma_len);
277    
278    
279     /* TODO: all this is just nonsense */
280    
281     n = 0;
282     while (rx_avail(d, port)) {
283     word[0] = word[1] = word[2] = word[3] = 0;
284     word[0] = word[1] = word[2] = word[3] =
285     rx_nextchar(d, port);
286     n++;
287     cpu->memory_rw(cpu, cpu->mem, addr, &word[0],
288     sizeof(word), MEM_WRITE, NO_EXCEPTIONS | PHYSICAL);
289    
290     addr += sizeof(word);
291     /* Half-page? */
292     if ((addr & 0x7fc) == 0)
293     break;
294     }
295     dev_scc_tick(cpu, extra);
296     return n*4;
297     }
298     }
299    
300    
301     /*
302     * dev_scc_access():
303     */
304 dpavlin 22 DEVICE_ACCESS(scc)
305 dpavlin 4 {
306     struct scc_data *d = (struct scc_data *) extra;
307     uint64_t idata = 0, odata = 0;
308     int port;
309     int ultrix_mode = 0;
310    
311 dpavlin 18 if (writeflag == MEM_WRITE)
312     idata = memory_readmax64(cpu, data, len);
313 dpavlin 4
314     /* relative_addr /= d->addrmul; */
315     /* See SGI comment below instead. */
316     /*
317     * SGI writes command to 0x0f, and data to 0x1f.
318     * (TODO: This works for port nr 0, how about port nr 1?)
319     */
320     if ((relative_addr & 0x0f) == 0xf) {
321     if (relative_addr == 0x0f)
322     relative_addr = 1;
323     else
324     relative_addr = 5;
325     }
326    
327     port = relative_addr / 8;
328     relative_addr &= 7;
329    
330     dev_scc_tick(cpu, extra);
331    
332     /*
333     * Ultrix writes words such as 0x1200 to relative address 0,
334     * instead of writing the byte 0x12 directly to address 1.
335     */
336     if ((relative_addr == 0 || relative_addr == 4) && (idata & 0xff) == 0) {
337     ultrix_mode = 1;
338     relative_addr ++;
339     idata >>= 8;
340     }
341    
342     switch (relative_addr) {
343     case 1: /* command */
344     if (writeflag==MEM_READ) {
345     odata = d->scc_register_r[port * N_SCC_REGS +
346     d->register_selected[port]];
347    
348     if (d->register_selected[port] == SCC_RR3) {
349     if (port == SCC_CHANNEL_B)
350     fatal("WARNING! scc channel B has "
351     "no RR3\n");
352    
353     d->scc_register_r[port * N_SCC_REGS +
354     SCC_RR3] = 0;
355     cpu_interrupt_ack(cpu, d->irq_nr);
356     }
357    
358     #ifdef SCC_DEBUG
359     fatal("[ scc: port %i, register %i, read value "
360     "0x%02x ]\n", port, d->register_selected[port],
361     (int)odata);
362     #endif
363     d->register_select_in_progress[port] = 0;
364     d->register_selected[port] = 0;
365     /* debug("[ scc: (port %i) read from 0x%08lx ]\n",
366     port, (long)relative_addr); */
367     } else {
368     /* If no register is selected, then select one.
369     Otherwise, write to the selected register. */
370     if (d->register_select_in_progress[port] == 0) {
371     d->register_select_in_progress[port] = 1;
372     d->register_selected[port] = idata;
373     d->register_selected[port] &= (N_SCC_REGS-1);
374     } else {
375     d->scc_register_w[port * N_SCC_REGS +
376     d->register_selected[port]] = idata;
377     #ifdef SCC_DEBUG
378     fatal("[ scc: port %i, register %i, write "
379     "value 0x%02x ]\n", port,
380     d->register_selected[port], idata);
381     #endif
382    
383     d->scc_register_r[port * N_SCC_REGS +
384     SCC_RR12] = d->scc_register_w[port *
385     N_SCC_REGS + SCC_WR12];
386     d->scc_register_r[port * N_SCC_REGS +
387     SCC_RR13] = d->scc_register_w[port *
388     N_SCC_REGS + SCC_WR13];
389    
390     d->register_select_in_progress[port] = 0;
391     d->register_selected[port] = 0;
392     }
393     }
394     break;
395     case 5: /* data */
396     if (writeflag==MEM_READ) {
397     if (rx_avail(d, port))
398     odata = rx_nextchar(d, port);
399    
400     /* TODO: perhaps only clear the RX part of RR3? */
401     d->scc_register_r[N_SCC_REGS + SCC_RR3] = 0;
402     cpu_interrupt_ack(cpu, d->irq_nr);
403    
404     debug("[ scc: (port %i) read from 0x%08lx: 0x%02x ]\n",
405     port, (long)relative_addr, (int)odata);
406     } else {
407     /* debug("[ scc: (port %i) write to 0x%08lx: "
408     "0x%08x ]\n", port, (long)relative_addr,
409     (int)idata); */
410    
411     /* Send the character: */
412     lk201_tx_data(&d->lk201, d->scc_nr * 2 + port, idata);
413    
414     /* Loopback: */
415     if (d->scc_register_w[port * N_SCC_REGS + SCC_WR14]
416     & SCC_WR14_LOCAL_LOOPB)
417     dev_scc_add_to_rx_queue(d, idata, d->scc_nr
418     * 2 + port);
419    
420     /* TX interrupt: */
421     if (d->scc_register_w[port * N_SCC_REGS + SCC_WR9] &
422     SCC_WR9_MASTER_IE &&
423     d->scc_register_w[port * N_SCC_REGS + SCC_WR1] &
424     SCC_WR1_TX_IE) {
425     if (port == SCC_CHANNEL_A)
426     d->scc_register_r[N_SCC_REGS + SCC_RR3]
427     |= SCC_RR3_TX_IP_A;
428     else
429     d->scc_register_r[N_SCC_REGS + SCC_RR3]
430     |= SCC_RR3_TX_IP_B;
431     }
432    
433     dev_scc_tick(cpu, extra);
434     }
435     break;
436     default:
437     if (writeflag==MEM_READ) {
438     debug("[ scc: (port %i) read from 0x%08lx ]\n",
439     port, (long)relative_addr);
440     } else {
441     debug("[ scc: (port %i) write to 0x%08lx: 0x%08x ]\n",
442     port, (long)relative_addr, (int)idata);
443     }
444     }
445    
446     if (ultrix_mode && writeflag == MEM_READ) {
447     odata <<= 8;
448     }
449    
450     if (writeflag == MEM_READ)
451     memory_writemax64(cpu, data, len, odata);
452    
453     return 1;
454     }
455    
456    
457     /*
458     * dev_scc_init():
459     *
460     * use_fb = non-zero when using graphical console + keyboard
461     * scc_nr = 0 or 1
462     * addmul = 1 in most cases, 8 on SGI?
463     */
464     void *dev_scc_init(struct machine *machine, struct memory *mem,
465     uint64_t baseaddr, int irq_nr, int use_fb, int scc_nr, int addrmul)
466     {
467     struct scc_data *d;
468    
469     d = malloc(sizeof(struct scc_data));
470     if (d == NULL) {
471     fprintf(stderr, "out of memory\n");
472     exit(1);
473     }
474     memset(d, 0, sizeof(struct scc_data));
475     d->irq_nr = irq_nr;
476     d->scc_nr = scc_nr;
477     d->use_fb = use_fb;
478     d->addrmul = addrmul;
479 dpavlin 22 d->console_handle = console_start_slave(machine, "SCC", 1);
480 dpavlin 4
481     lk201_init(&d->lk201, use_fb, dev_scc_add_to_rx_queue,
482     d->console_handle, d);
483    
484     memory_device_register(mem, "scc", baseaddr, DEV_SCC_LENGTH,
485 dpavlin 20 dev_scc_access, d, DM_DEFAULT, NULL);
486 dpavlin 4 machine_add_tickfunction(machine, dev_scc_tick, d, SCC_TICK_SHIFT);
487    
488     return (void *) d;
489     }
490    

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