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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_pmppc.c,v 1.2 2005/02/15 06:25:34 debug Exp $ |
* $Id: dev_pmppc.c,v 1.8 2007/01/29 18:06:52 debug Exp $ |
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* |
* |
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* PM/PPC devices. |
* PM/PPC devices. |
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* |
* |
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#include <string.h> |
#include <string.h> |
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#include "cpu.h" |
#include "cpu.h" |
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#include "devices.h" |
#include "device.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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}; |
}; |
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/* |
DEVICE_ACCESS(pmppc_board) |
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* dev_pmppc_board_access(): |
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*/ |
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int dev_pmppc_board_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, |
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void *extra) |
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{ |
{ |
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struct pmppc_data *d = extra; |
struct pmppc_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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idata = memory_readmax64(cpu, data, len); |
if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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relative_addr += PMPPC_CONFIG0; |
relative_addr += PMPPC_CONFIG0; |
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} |
} |
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/* |
DEVINIT(pmppc) |
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* dev_pmppc_init(): |
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*/ |
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void dev_pmppc_init(struct memory *mem) |
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{ |
{ |
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struct pmppc_data *d; |
struct pmppc_data *d; |
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struct memory *mem = devinit->machine->memory; |
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d = malloc(sizeof(struct pmppc_data)); |
d = malloc(sizeof(struct pmppc_data)); |
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if (d == NULL) { |
if (d == NULL) { |
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* config0: |
* config0: |
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* bit 7 Is monarch (?). |
* bit 7 Is monarch (?). |
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* bit 5 Has ethernet. |
* bit 5 Has ethernet. |
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* bit 4 Has RTC. |
* bit 4 1 = No RTC. |
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* bits 3..2 Flash size (00 = 256 MB, 01 = 128 MB, |
* bits 3..2 Flash size (00 = 256 MB, 01 = 128 MB, |
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* 10 = 64 MB, 11 = 32 MB). |
* 10 = 64 MB, 11 = 32 MB). |
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* bits 1..0 Flash width (00 = 64, 01 = 32, 10 = 16, 11 = 0). |
* bits 1..0 Flash width (00 = 64, 01 = 32, 10 = 16, 11 = 0). |
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* bits 1..0 Bus frequency: 00 = 66.66 MHz, 01 = 83.33 MHz, |
* bits 1..0 Bus frequency: 00 = 66.66 MHz, 01 = 83.33 MHz, |
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* 10 = 100.00 MHz, 11 = reserved? |
* 10 = 100.00 MHz, 11 = reserved? |
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*/ |
*/ |
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d->config0 = 0x30; |
d->config0 = 0x20; |
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d->config1 = 0; /* TODO */ |
d->config1 = 0; |
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if (mem->physical_max == 32*1048576) { |
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} else if (mem->physical_max == 64*1048576) { |
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d->config1 |= 0x01; |
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} else if (mem->physical_max == 128*1048576) { |
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d->config1 |= 0x10; |
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} else if (mem->physical_max == 256*1048576) { |
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d->config1 |= 0x11; |
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} else { |
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fatal("A PM/PPC can have 32, 64, 128, or 256 MB RAM.\n"); |
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exit(1); |
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} |
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memory_device_register(mem, "pmppc_board", |
memory_device_register(mem, "pmppc_board", |
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PMPPC_CONFIG0, 0x10, dev_pmppc_board_access, d, MEM_DEFAULT, NULL); |
PMPPC_CONFIG0, 0x10, dev_pmppc_board_access, d, DM_DEFAULT, NULL); |
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return 1; |
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} |
} |
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