| 1 |
/* |
| 2 |
* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
| 3 |
* |
| 4 |
* Redistribution and use in source and binary forms, with or without |
| 5 |
* modification, are permitted provided that the following conditions are met: |
| 6 |
* |
| 7 |
* 1. Redistributions of source code must retain the above copyright |
| 8 |
* notice, this list of conditions and the following disclaimer. |
| 9 |
* 2. Redistributions in binary form must reproduce the above copyright |
| 10 |
* notice, this list of conditions and the following disclaimer in the |
| 11 |
* documentation and/or other materials provided with the distribution. |
| 12 |
* 3. The name of the author may not be used to endorse or promote products |
| 13 |
* derived from this software without specific prior written permission. |
| 14 |
* |
| 15 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 16 |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 18 |
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 19 |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 20 |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 21 |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 22 |
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 23 |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 24 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 25 |
* SUCH DAMAGE. |
| 26 |
* |
| 27 |
* |
| 28 |
* $Id: dev_rd94.c,v 1.25 2005/10/26 14:37:04 debug Exp $ |
| 29 |
* |
| 30 |
* Used by NEC-RD94, -R94, and -R96. |
| 31 |
*/ |
| 32 |
|
| 33 |
#include <stdio.h> |
| 34 |
#include <stdlib.h> |
| 35 |
#include <string.h> |
| 36 |
|
| 37 |
#include "bus_pci.h" |
| 38 |
#include "cop0.h" |
| 39 |
#include "cpu.h" |
| 40 |
#include "cpu_mips.h" |
| 41 |
#include "device.h" |
| 42 |
#include "machine.h" |
| 43 |
#include "memory.h" |
| 44 |
#include "misc.h" |
| 45 |
|
| 46 |
#include "rd94.h" |
| 47 |
|
| 48 |
|
| 49 |
#define RD94_TICK_SHIFT 14 |
| 50 |
|
| 51 |
#define DEV_RD94_LENGTH 0x1000 |
| 52 |
|
| 53 |
struct rd94_data { |
| 54 |
struct pci_data *pci_data; |
| 55 |
uint32_t reg[DEV_RD94_LENGTH / 4]; |
| 56 |
int pciirq; |
| 57 |
|
| 58 |
int intmask; |
| 59 |
int interval; |
| 60 |
int interval_start; |
| 61 |
}; |
| 62 |
|
| 63 |
|
| 64 |
/* |
| 65 |
* dev_rd94_tick(): |
| 66 |
*/ |
| 67 |
void dev_rd94_tick(struct cpu *cpu, void *extra) |
| 68 |
{ |
| 69 |
struct rd94_data *d = extra; |
| 70 |
|
| 71 |
/* TODO: hm... intmask !=0 ? */ |
| 72 |
if (d->interval_start > 0 && d->interval > 0 && d->intmask != 0) { |
| 73 |
d->interval --; |
| 74 |
if (d->interval <= 0) { |
| 75 |
debug("[ rd94: interval timer interrupt ]\n"); |
| 76 |
cpu_interrupt(cpu, 5); |
| 77 |
} |
| 78 |
} |
| 79 |
} |
| 80 |
|
| 81 |
|
| 82 |
/* |
| 83 |
* dev_rd94_access(): |
| 84 |
*/ |
| 85 |
int dev_rd94_access(struct cpu *cpu, struct memory *mem, |
| 86 |
uint64_t relative_addr, unsigned char *data, size_t len, |
| 87 |
int writeflag, void *extra) |
| 88 |
{ |
| 89 |
struct rd94_data *d = (struct rd94_data *) extra; |
| 90 |
uint64_t idata = 0, odata = 0; |
| 91 |
int regnr; |
| 92 |
|
| 93 |
if (writeflag == MEM_WRITE) |
| 94 |
idata = memory_readmax64(cpu, data, len); |
| 95 |
|
| 96 |
regnr = relative_addr / sizeof(uint32_t); |
| 97 |
|
| 98 |
switch (relative_addr) { |
| 99 |
case RD94_SYS_CONFIG: |
| 100 |
if (writeflag == MEM_WRITE) { |
| 101 |
fatal("[ rd94: write to CONFIG: 0x%llx ]\n", |
| 102 |
(long long)idata); |
| 103 |
} else { |
| 104 |
odata = 0; |
| 105 |
fatal("[ rd94: read from CONFIG: 0x%llx ]\n", |
| 106 |
(long long)odata); |
| 107 |
} |
| 108 |
break; |
| 109 |
case RD94_SYS_INTSTAT1: /* LB (Local Bus ???) */ |
| 110 |
if (writeflag == MEM_WRITE) { |
| 111 |
} else { |
| 112 |
/* Return value is (irq level + 1) << 2 */ |
| 113 |
odata = (8+1) << 2; |
| 114 |
|
| 115 |
/* Ugly hack: */ |
| 116 |
if ((cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] & 0x800) |
| 117 |
== 0) |
| 118 |
odata = 0; |
| 119 |
} |
| 120 |
debug("[ rd94: intstat1 ]\n"); |
| 121 |
/* cpu_interrupt_ack(cpu, 3); */ |
| 122 |
break; |
| 123 |
case RD94_SYS_INTSTAT2: /* PCI/EISA */ |
| 124 |
if (writeflag == MEM_WRITE) { |
| 125 |
} else { |
| 126 |
odata = 0; /* TODO */ |
| 127 |
} |
| 128 |
debug("[ rd94: intstat2 ]\n"); |
| 129 |
/* cpu_interrupt_ack(cpu, 4); */ |
| 130 |
break; |
| 131 |
case RD94_SYS_INTSTAT3: /* IT (Interval Timer) */ |
| 132 |
if (writeflag == MEM_WRITE) { |
| 133 |
} else { |
| 134 |
odata = 0; /* return value does not matter? */ |
| 135 |
} |
| 136 |
debug("[ rd94: intstat3 ]\n"); |
| 137 |
cpu_interrupt_ack(cpu, 5); |
| 138 |
d->interval = d->interval_start; |
| 139 |
break; |
| 140 |
case RD94_SYS_INTSTAT4: /* IPI */ |
| 141 |
if (writeflag == MEM_WRITE) { |
| 142 |
} else { |
| 143 |
odata = 0; /* return value does not matter? */ |
| 144 |
} |
| 145 |
fatal("[ rd94: intstat4 ]\n"); |
| 146 |
cpu_interrupt_ack(cpu, 6); |
| 147 |
break; |
| 148 |
case RD94_SYS_CPUID: |
| 149 |
if (writeflag == MEM_WRITE) { |
| 150 |
fatal("[ rd94: write to CPUID: 0x%llx ]\n", |
| 151 |
(long long)idata); |
| 152 |
} else { |
| 153 |
odata = cpu->cpu_id; |
| 154 |
fatal("[ rd94: read from CPUID: 0x%llx ]\n", |
| 155 |
(long long)odata); |
| 156 |
} |
| 157 |
break; |
| 158 |
case RD94_SYS_EXT_IMASK: |
| 159 |
if (writeflag == MEM_WRITE) { |
| 160 |
d->intmask = idata; |
| 161 |
} else { |
| 162 |
odata = d->intmask; |
| 163 |
} |
| 164 |
break; |
| 165 |
case RD94_SYS_IT_VALUE: |
| 166 |
if (writeflag == MEM_WRITE) { |
| 167 |
d->interval = d->interval_start = idata; |
| 168 |
debug("[ rd94: setting Interval Timer value to %i ]\n", |
| 169 |
(int)idata); |
| 170 |
} else { |
| 171 |
odata = d->interval_start; |
| 172 |
/* TODO: or d->interval ? */; |
| 173 |
} |
| 174 |
break; |
| 175 |
case RD94_SYS_PCI_CONFADDR: |
| 176 |
case RD94_SYS_PCI_CONFDATA: |
| 177 |
if (writeflag == MEM_WRITE) { |
| 178 |
bus_pci_access(cpu, mem, relative_addr == |
| 179 |
RD94_SYS_PCI_CONFADDR? BUS_PCI_ADDR : BUS_PCI_DATA, |
| 180 |
&idata, writeflag, d->pci_data); |
| 181 |
} else { |
| 182 |
bus_pci_access(cpu, mem, relative_addr == |
| 183 |
RD94_SYS_PCI_CONFADDR? BUS_PCI_ADDR : BUS_PCI_DATA, |
| 184 |
&odata, writeflag, d->pci_data); |
| 185 |
/* odata = 0; */ |
| 186 |
} |
| 187 |
break; |
| 188 |
default: |
| 189 |
if (writeflag == MEM_WRITE) { |
| 190 |
fatal("[ rd94: unimplemented write to address 0x%x, " |
| 191 |
"data=0x%02x ]\n", (int)relative_addr, (int)idata); |
| 192 |
} else { |
| 193 |
fatal("[ rd94: unimplemented read from address 0x%x" |
| 194 |
" ]\n", (int)relative_addr); |
| 195 |
} |
| 196 |
} |
| 197 |
|
| 198 |
if (writeflag == MEM_READ) |
| 199 |
memory_writemax64(cpu, data, len, odata); |
| 200 |
|
| 201 |
return 1; |
| 202 |
} |
| 203 |
|
| 204 |
|
| 205 |
/* |
| 206 |
* devinit_rd94(): |
| 207 |
*/ |
| 208 |
int devinit_rd94(struct devinit *devinit) |
| 209 |
{ |
| 210 |
struct rd94_data *d = malloc(sizeof(struct rd94_data)); |
| 211 |
if (d == NULL) { |
| 212 |
fprintf(stderr, "out of memory\n"); |
| 213 |
exit(1); |
| 214 |
} |
| 215 |
memset(d, 0, sizeof(struct rd94_data)); |
| 216 |
d->pciirq = devinit->irq_nr; |
| 217 |
d->pci_data = bus_pci_init(d->pciirq); |
| 218 |
|
| 219 |
memory_device_register(devinit->machine->memory, devinit->name, |
| 220 |
devinit->addr, DEV_RD94_LENGTH, |
| 221 |
dev_rd94_access, (void *)d, MEM_DEFAULT, NULL); |
| 222 |
|
| 223 |
machine_add_tickfunction(devinit->machine, dev_rd94_tick, |
| 224 |
d, RD94_TICK_SHIFT); |
| 225 |
|
| 226 |
devinit->return_ptr = d->pci_data; |
| 227 |
|
| 228 |
return 1; |
| 229 |
} |
| 230 |
|
Parent Directory
| 
Revision Log