/[gxemul]/trunk/src/devices/dev_rd94.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/devices/dev_rd94.c

Parent Directory Parent Directory | Revision Log Revision Log


Revision 30 - (show annotations)
Mon Oct 8 16:20:40 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 5839 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1325 2006/08/15 15:38:37 debug Exp $
20060723	More Transputer instructions (pfix, nfix, opr, mint, ldl, ldlp,
		eqc, rev, ajw, stl, stlf, sthf, sub, ldnl, ldnlp, ldpi, move,
		wcnt, add, bcnt).
		Adding more SPARC instructions (andcc, addcc, bl, rdpr).
		Progress on the igsfb framebuffer used by NetBSD/netwinder.
		Enabling 8-bit fills in dev_fb.
		NetBSD/netwinder 3.0.1 can now run from a disk image :-)
20060724	Cleanup/performance fix for 64-bit virtual translation table
		updates (by removing the "timestamp" stuff). A full NetBSD/pmax
		3.0.1 install for R4400 has dropped from 667 seconds to 584 :)
		Fixing the igsfb "almost vga" color (it is 24-bit, not 18-bit).
		Adding some MIPS instruction combinations (3*lw, and 3*addu).
		The 8048 keyboard now turns off interrupt enable between the
		KBR_ACK and the KBR_RSTDONE, to work better with Linux 2.6.
		Not causing PPC DEC interrupts if PPC_NO_DEC is set for a
		specific CPU; NetBSD/bebox gets slightly further than before.
		Adding some more SPARC instructions: branches, udiv.
20060725	Refreshing dev_pckbc.c a little.
		Cleanups for the SH emulation mode, and adding the first
		"compact" (16-bit) instructions: various simple movs, nop,
		shll, stc, or, ldc.
20060726	Adding dummy "pcn" (AMD PCnet NIC) PCI glue.
20060727	Various cleanups; removing stuff from cpu.h, such as
		running_translated (not really meaningful anymore), and
		page flags (breaking into the debugger clears all translations
		anyway).
		Minor MIPS instruction combination updates.
20060807	Expanding the 3*sw and 3*lw MIPS instruction combinations to
		work with 2* and 4* too, resulting in a minor performance gain.
		Implementing a usleep hack for the RM52xx/MIPS32/MIPS64 "wait"
		instruction (when emulating 1 cpu).
20060808	Experimenting with some more MIPS instruction combinations.
		Implementing support for showing a (hardcoded 12x22) text
		cursor in igsfb.
20060809	Simplifying the NetBSD/evbmips (Malta) install instructions
		somewhat (by using a NetBSD/pmax ramdisk install kernel).
20060812	Experimenting more with the MIPS 'wait' instruction.
		PCI configuration register writes can now be handled, which
		allow PCI IDE controllers to work with NetBSD/Malta 3.0.1 and
		NetBSD/cobalt 3.0.1. (Previously only NetBSD 2.1 worked.)
20060813	Updating dev_gt.c based on numbers from Alec Voropay, to enable
		Linux 2.6 to use PCI on Malta.
		Continuing on Algor interrupt stuff.
20060814	Adding support for routing ISA interrupts to two different
		interrupts, making it possible to run NetBSD/algor :-)
20060814-15	Testing for the release.

==============  RELEASE 0.4.2  ==============


1 /*
2 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_rd94.c,v 1.36 2006/07/23 14:37:34 debug Exp $
29 *
30 * Used by NEC-RD94, -R94, and -R96.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36
37 #include "bus_pci.h"
38 #include "cop0.h"
39 #include "cpu.h"
40 #include "cpu_mips.h"
41 #include "device.h"
42 #include "machine.h"
43 #include "memory.h"
44 #include "misc.h"
45
46 #include "rd94.h"
47
48
49 #define RD94_TICK_SHIFT 14
50
51 #define DEV_RD94_LENGTH 0x1000
52
53 struct rd94_data {
54 struct pci_data *pci_data;
55 uint32_t reg[DEV_RD94_LENGTH / 4];
56 int pciirq;
57
58 int intmask;
59 int interval;
60 int interval_start;
61 };
62
63
64 DEVICE_TICK(rd94)
65 {
66 struct rd94_data *d = extra;
67
68 /* TODO: hm... intmask !=0 ? */
69 if (d->interval_start > 0 && d->interval > 0 && d->intmask != 0) {
70 d->interval --;
71 if (d->interval <= 0) {
72 debug("[ rd94: interval timer interrupt ]\n");
73 cpu_interrupt(cpu, 5);
74 }
75 }
76 }
77
78
79 DEVICE_ACCESS(rd94)
80 {
81 struct rd94_data *d = (struct rd94_data *) extra;
82 uint64_t idata = 0, odata = 0;
83 int regnr, bus, dev, func, pcireg;
84
85 if (writeflag == MEM_WRITE)
86 idata = memory_readmax64(cpu, data, len);
87
88 regnr = relative_addr / sizeof(uint32_t);
89
90 switch (relative_addr) {
91
92 case RD94_SYS_CONFIG:
93 if (writeflag == MEM_WRITE) {
94 fatal("[ rd94: write to CONFIG: 0x%llx ]\n",
95 (long long)idata);
96 } else {
97 odata = 0;
98 fatal("[ rd94: read from CONFIG: 0x%llx ]\n",
99 (long long)odata);
100 }
101 break;
102
103 case RD94_SYS_INTSTAT1: /* LB (Local Bus ???) */
104 if (writeflag == MEM_WRITE) {
105 } else {
106 /* Return value is (irq level + 1) << 2 */
107 odata = (8+1) << 2;
108
109 /* Ugly hack: */
110 if ((cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] & 0x800)
111 == 0)
112 odata = 0;
113 }
114 debug("[ rd94: intstat1 ]\n");
115 /* cpu_interrupt_ack(cpu, 3); */
116 break;
117
118 case RD94_SYS_INTSTAT2: /* PCI/EISA */
119 if (writeflag == MEM_WRITE) {
120 } else {
121 odata = 0; /* TODO */
122 }
123 debug("[ rd94: intstat2 ]\n");
124 /* cpu_interrupt_ack(cpu, 4); */
125 break;
126
127 case RD94_SYS_INTSTAT3: /* IT (Interval Timer) */
128 if (writeflag == MEM_WRITE) {
129 } else {
130 odata = 0; /* return value does not matter? */
131 }
132 debug("[ rd94: intstat3 ]\n");
133 cpu_interrupt_ack(cpu, 5);
134 d->interval = d->interval_start;
135 break;
136
137 case RD94_SYS_INTSTAT4: /* IPI */
138 if (writeflag == MEM_WRITE) {
139 } else {
140 odata = 0; /* return value does not matter? */
141 }
142 fatal("[ rd94: intstat4 ]\n");
143 cpu_interrupt_ack(cpu, 6);
144 break;
145
146 case RD94_SYS_CPUID:
147 if (writeflag == MEM_WRITE) {
148 fatal("[ rd94: write to CPUID: 0x%llx ]\n",
149 (long long)idata);
150 } else {
151 odata = cpu->cpu_id;
152 fatal("[ rd94: read from CPUID: 0x%llx ]\n",
153 (long long)odata);
154 }
155 break;
156
157 case RD94_SYS_EXT_IMASK:
158 if (writeflag == MEM_WRITE) {
159 d->intmask = idata;
160 } else {
161 odata = d->intmask;
162 }
163 break;
164
165 case RD94_SYS_IT_VALUE:
166 if (writeflag == MEM_WRITE) {
167 d->interval = d->interval_start = idata;
168 debug("[ rd94: setting Interval Timer value to %i ]\n",
169 (int)idata);
170 } else {
171 odata = d->interval_start;
172 /* TODO: or d->interval ? */;
173 }
174 break;
175
176 case RD94_SYS_PCI_CONFADDR:
177 bus_pci_decompose_1(idata, &bus, &dev, &func, &pcireg);
178 bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, pcireg);
179 break;
180
181 case RD94_SYS_PCI_CONFDATA:
182 bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
183 &odata : &idata, len, writeflag);
184 break;
185
186 default:if (writeflag == MEM_WRITE) {
187 fatal("[ rd94: unimplemented write to address 0x%x, "
188 "data=0x%02x ]\n", (int)relative_addr, (int)idata);
189 } else {
190 fatal("[ rd94: unimplemented read from address 0x%x"
191 " ]\n", (int)relative_addr);
192 }
193 }
194
195 if (writeflag == MEM_READ)
196 memory_writemax64(cpu, data, len, odata);
197
198 return 1;
199 }
200
201
202 DEVINIT(rd94)
203 {
204 struct rd94_data *d = malloc(sizeof(struct rd94_data));
205 if (d == NULL) {
206 fprintf(stderr, "out of memory\n");
207 exit(1);
208 }
209 memset(d, 0, sizeof(struct rd94_data));
210 d->pciirq = devinit->irq_nr;
211 d->pci_data = bus_pci_init(devinit->machine, d->pciirq,
212 0,0, 0,0,0, 0,0,0);
213
214 memory_device_register(devinit->machine->memory, devinit->name,
215 devinit->addr, DEV_RD94_LENGTH,
216 dev_rd94_access, (void *)d, DM_DEFAULT, NULL);
217
218 machine_add_tickfunction(devinit->machine, dev_rd94_tick,
219 d, RD94_TICK_SHIFT, 0.0);
220
221 devinit->return_ptr = d->pci_data;
222
223 return 1;
224 }
225

  ViewVC Help
Powered by ViewVC 1.1.26