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/* |
/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_rd94.c,v 1.29 2005/11/21 09:17:27 debug Exp $ |
* $Id: dev_rd94.c,v 1.34 2006/02/09 20:02:59 debug Exp $ |
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* |
* |
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* Used by NEC-RD94, -R94, and -R96. |
* Used by NEC-RD94, -R94, and -R96. |
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*/ |
*/ |
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/* |
/* |
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* dev_rd94_access(): |
* dev_rd94_access(): |
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*/ |
*/ |
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int dev_rd94_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(rd94) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
{ |
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struct rd94_data *d = (struct rd94_data *) extra; |
struct rd94_data *d = (struct rd94_data *) extra; |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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int regnr; |
int regnr, bus, dev, func, pcireg; |
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|
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
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regnr = relative_addr / sizeof(uint32_t); |
regnr = relative_addr / sizeof(uint32_t); |
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|
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switch (relative_addr) { |
switch (relative_addr) { |
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case RD94_SYS_CONFIG: |
case RD94_SYS_CONFIG: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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fatal("[ rd94: write to CONFIG: 0x%llx ]\n", |
fatal("[ rd94: write to CONFIG: 0x%llx ]\n", |
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(long long)odata); |
(long long)odata); |
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} |
} |
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break; |
break; |
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|
|
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case RD94_SYS_INTSTAT1: /* LB (Local Bus ???) */ |
case RD94_SYS_INTSTAT1: /* LB (Local Bus ???) */ |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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} else { |
} else { |
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debug("[ rd94: intstat1 ]\n"); |
debug("[ rd94: intstat1 ]\n"); |
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/* cpu_interrupt_ack(cpu, 3); */ |
/* cpu_interrupt_ack(cpu, 3); */ |
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break; |
break; |
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case RD94_SYS_INTSTAT2: /* PCI/EISA */ |
case RD94_SYS_INTSTAT2: /* PCI/EISA */ |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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} else { |
} else { |
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debug("[ rd94: intstat2 ]\n"); |
debug("[ rd94: intstat2 ]\n"); |
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/* cpu_interrupt_ack(cpu, 4); */ |
/* cpu_interrupt_ack(cpu, 4); */ |
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break; |
break; |
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|
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case RD94_SYS_INTSTAT3: /* IT (Interval Timer) */ |
case RD94_SYS_INTSTAT3: /* IT (Interval Timer) */ |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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} else { |
} else { |
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cpu_interrupt_ack(cpu, 5); |
cpu_interrupt_ack(cpu, 5); |
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d->interval = d->interval_start; |
d->interval = d->interval_start; |
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break; |
break; |
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|
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case RD94_SYS_INTSTAT4: /* IPI */ |
case RD94_SYS_INTSTAT4: /* IPI */ |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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} else { |
} else { |
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fatal("[ rd94: intstat4 ]\n"); |
fatal("[ rd94: intstat4 ]\n"); |
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cpu_interrupt_ack(cpu, 6); |
cpu_interrupt_ack(cpu, 6); |
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break; |
break; |
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|
|
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case RD94_SYS_CPUID: |
case RD94_SYS_CPUID: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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fatal("[ rd94: write to CPUID: 0x%llx ]\n", |
fatal("[ rd94: write to CPUID: 0x%llx ]\n", |
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(long long)odata); |
(long long)odata); |
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} |
} |
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break; |
break; |
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|
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case RD94_SYS_EXT_IMASK: |
case RD94_SYS_EXT_IMASK: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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d->intmask = idata; |
d->intmask = idata; |
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odata = d->intmask; |
odata = d->intmask; |
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} |
} |
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break; |
break; |
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|
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case RD94_SYS_IT_VALUE: |
case RD94_SYS_IT_VALUE: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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d->interval = d->interval_start = idata; |
d->interval = d->interval_start = idata; |
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/* TODO: or d->interval ? */; |
/* TODO: or d->interval ? */; |
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} |
} |
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break; |
break; |
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|
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case RD94_SYS_PCI_CONFADDR: |
case RD94_SYS_PCI_CONFADDR: |
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bus_pci_decompose_1(idata, &bus, &dev, &func, &pcireg); |
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, pcireg); |
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break; |
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|
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case RD94_SYS_PCI_CONFDATA: |
case RD94_SYS_PCI_CONFDATA: |
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if (writeflag == MEM_WRITE) { |
bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? |
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bus_pci_access(cpu, mem, relative_addr == |
&odata : &idata, len, writeflag); |
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RD94_SYS_PCI_CONFADDR? BUS_PCI_ADDR : BUS_PCI_DATA, |
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&idata, len, writeflag, d->pci_data); |
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} else { |
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bus_pci_access(cpu, mem, relative_addr == |
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RD94_SYS_PCI_CONFADDR? BUS_PCI_ADDR : BUS_PCI_DATA, |
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&odata, len, writeflag, d->pci_data); |
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} |
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break; |
break; |
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default: |
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if (writeflag == MEM_WRITE) { |
default:if (writeflag == MEM_WRITE) { |
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fatal("[ rd94: unimplemented write to address 0x%x, " |
fatal("[ rd94: unimplemented write to address 0x%x, " |
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"data=0x%02x ]\n", (int)relative_addr, (int)idata); |
"data=0x%02x ]\n", (int)relative_addr, (int)idata); |
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} else { |
} else { |
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} |
} |
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/* |
DEVINIT(rd94) |
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* devinit_rd94(): |
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*/ |
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int devinit_rd94(struct devinit *devinit) |
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{ |
{ |
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struct rd94_data *d = malloc(sizeof(struct rd94_data)); |
struct rd94_data *d = malloc(sizeof(struct rd94_data)); |
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if (d == NULL) { |
if (d == NULL) { |
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} |
} |
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memset(d, 0, sizeof(struct rd94_data)); |
memset(d, 0, sizeof(struct rd94_data)); |
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d->pciirq = devinit->irq_nr; |
d->pciirq = devinit->irq_nr; |
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d->pci_data = bus_pci_init(d->pciirq, 0,0, 0,0,0, 0,0,0); |
d->pci_data = bus_pci_init(devinit->machine, d->pciirq, |
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0,0, 0,0,0, 0,0,0); |
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memory_device_register(devinit->machine->memory, devinit->name, |
memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, DEV_RD94_LENGTH, |
devinit->addr, DEV_RD94_LENGTH, |