src/devices/dev_rd94.c

/*
 *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_rd94.c,v 1.36 2006/07/23 14:37:34 debug Exp $
 *  
 *  Used by NEC-RD94, -R94, and -R96.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "bus_pci.h"
#include "cop0.h"
#include "cpu.h"
#include "cpu_mips.h"
#include "device.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"

#include "rd94.h"


#define RD94_TICK_SHIFT         14

#define DEV_RD94_LENGTH         0x1000

struct rd94_data {
        struct pci_data *pci_data;
        uint32_t        reg[DEV_RD94_LENGTH / 4];
        int             pciirq;

        int             intmask;
        int             interval;
        int             interval_start;
};


DEVICE_TICK(rd94)
{
        struct rd94_data *d = extra;

        /*  TODO: hm... intmask !=0 ?  */
        if (d->interval_start > 0 && d->interval > 0 && d->intmask != 0) {
                d->interval --;
                if (d->interval <= 0) {
                        debug("[ rd94: interval timer interrupt ]\n");
                        cpu_interrupt(cpu, 5);
                }
        }
}


DEVICE_ACCESS(rd94)
{
        struct rd94_data *d = (struct rd94_data *) extra;
        uint64_t idata = 0, odata = 0;
        int regnr, bus, dev, func, pcireg;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        regnr = relative_addr / sizeof(uint32_t);

        switch (relative_addr) {

        case RD94_SYS_CONFIG:
                if (writeflag == MEM_WRITE) {
                        fatal("[ rd94: write to CONFIG: 0x%llx ]\n",
                            (long long)idata);
                } else {
                        odata = 0;
                        fatal("[ rd94: read from CONFIG: 0x%llx ]\n",
                            (long long)odata);
                }
                break;

        case RD94_SYS_INTSTAT1:         /*  LB (Local Bus ???)  */
                if (writeflag == MEM_WRITE) {
                } else {
                        /*  Return value is (irq level + 1) << 2  */
                        odata = (8+1) << 2;

                        /*  Ugly hack:  */
                        if ((cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] & 0x800)
                            == 0)
                                odata = 0;
                }
                debug("[ rd94: intstat1 ]\n");
/*              cpu_interrupt_ack(cpu, 3); */
                break;

        case RD94_SYS_INTSTAT2:         /*  PCI/EISA  */
                if (writeflag == MEM_WRITE) {
                } else {
                        odata = 0;      /*  TODO  */
                }
                debug("[ rd94: intstat2 ]\n");
/*              cpu_interrupt_ack(cpu, 4); */
                break;

        case RD94_SYS_INTSTAT3:         /*  IT (Interval Timer)  */
                if (writeflag == MEM_WRITE) {
                } else {
                        odata = 0;      /*  return value does not matter?  */
                }
                debug("[ rd94: intstat3 ]\n");
                cpu_interrupt_ack(cpu, 5);
                d->interval = d->interval_start;
                break;

        case RD94_SYS_INTSTAT4:         /*  IPI  */
                if (writeflag == MEM_WRITE) {
                } else {
                        odata = 0;      /*  return value does not matter?  */
                }
                fatal("[ rd94: intstat4 ]\n");
                cpu_interrupt_ack(cpu, 6);
                break;

        case RD94_SYS_CPUID:
                if (writeflag == MEM_WRITE) {
                        fatal("[ rd94: write to CPUID: 0x%llx ]\n",
                            (long long)idata);
                } else {
                        odata = cpu->cpu_id;
                        fatal("[ rd94: read from CPUID: 0x%llx ]\n",
                            (long long)odata);
                }
                break;

        case RD94_SYS_EXT_IMASK:
                if (writeflag == MEM_WRITE) {
                        d->intmask = idata;
                } else {
                        odata = d->intmask;
                }
                break;

        case RD94_SYS_IT_VALUE:
                if (writeflag == MEM_WRITE) {
                        d->interval = d->interval_start = idata;
                        debug("[ rd94: setting Interval Timer value to %i ]\n",
                            (int)idata);
                } else {
                        odata = d->interval_start;
                        /*  TODO: or d->interval ?  */;
                }
                break;

        case RD94_SYS_PCI_CONFADDR:
                bus_pci_decompose_1(idata, &bus, &dev, &func, &pcireg);
                bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, pcireg);
                break;

        case RD94_SYS_PCI_CONFDATA:
                bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
                    &odata : &idata, len, writeflag);
                break;

        default:if (writeflag == MEM_WRITE) {
                        fatal("[ rd94: unimplemented write to address 0x%x, "
                            "data=0x%02x ]\n", (int)relative_addr, (int)idata);
                } else {
                        fatal("[ rd94: unimplemented read from address 0x%x"
                            " ]\n", (int)relative_addr);
                }
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


DEVINIT(rd94)
{
        struct rd94_data *d = malloc(sizeof(struct rd94_data));
        if (d == NULL) {
                fprintf(stderr, "out of memory\n");
                exit(1);
        }
        memset(d, 0, sizeof(struct rd94_data));
        d->pciirq   = devinit->irq_nr;
        d->pci_data = bus_pci_init(devinit->machine, d->pciirq,
            0,0, 0,0,0, 0,0,0);

        memory_device_register(devinit->machine->memory, devinit->name,
            devinit->addr, DEV_RD94_LENGTH,
            dev_rd94_access, (void *)d, DM_DEFAULT, NULL);

        machine_add_tickfunction(devinit->machine, dev_rd94_tick,
            d, RD94_TICK_SHIFT, 0.0);

        devinit->return_ptr = d->pci_data;

        return 1;
}

1	dpavlin	4	/*
2	dpavlin	22	* Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3	dpavlin	4	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	30	* $Id: dev_rd94.c,v 1.36 2006/07/23 14:37:34 debug Exp $
29	dpavlin	4	*
30			* Used by NEC-RD94, -R94, and -R96.
31			*/
32
33			#include <stdio.h>
34			#include <stdlib.h>
35			#include <string.h>
36
37			#include "bus_pci.h"
38			#include "cop0.h"
39			#include "cpu.h"
40			#include "cpu_mips.h"
41			#include "device.h"
42			#include "machine.h"
43			#include "memory.h"
44			#include "misc.h"
45
46			#include "rd94.h"
47
48
49			#define RD94_TICK_SHIFT 14
50
51			#define DEV_RD94_LENGTH 0x1000
52
53			struct rd94_data {
54			struct pci_data *pci_data;
55			uint32_t reg[DEV_RD94_LENGTH / 4];
56			int pciirq;
57
58			int intmask;
59			int interval;
60			int interval_start;
61			};
62
63
64	dpavlin	30	DEVICE_TICK(rd94)
65	dpavlin	4	{
66			struct rd94_data *d = extra;
67
68			/* TODO: hm... intmask !=0 ? */
69			if (d->interval_start > 0 && d->interval > 0 && d->intmask != 0) {
70			d->interval --;
71			if (d->interval <= 0) {
72			debug("[ rd94: interval timer interrupt ]\n");
73			cpu_interrupt(cpu, 5);
74			}
75			}
76			}
77
78
79	dpavlin	22	DEVICE_ACCESS(rd94)
80	dpavlin	4	{
81			struct rd94_data d = (struct rd94_data ) extra;
82			uint64_t idata = 0, odata = 0;
83	dpavlin	22	int regnr, bus, dev, func, pcireg;
84	dpavlin	4
85	dpavlin	18	if (writeflag == MEM_WRITE)
86			idata = memory_readmax64(cpu, data, len);
87
88	dpavlin	4	regnr = relative_addr / sizeof(uint32_t);
89
90			switch (relative_addr) {
91	dpavlin	22
92	dpavlin	4	case RD94_SYS_CONFIG:
93			if (writeflag == MEM_WRITE) {
94			fatal("[ rd94: write to CONFIG: 0x%llx ]\n",
95			(long long)idata);
96			} else {
97			odata = 0;
98			fatal("[ rd94: read from CONFIG: 0x%llx ]\n",
99			(long long)odata);
100			}
101			break;
102	dpavlin	22
103	dpavlin	4	case RD94_SYS_INTSTAT1: /* LB (Local Bus ???) */
104			if (writeflag == MEM_WRITE) {
105			} else {
106			/* Return value is (irq level + 1) << 2 */
107			odata = (8+1) << 2;
108
109			/* Ugly hack: */
110			if ((cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] & 0x800)
111			== 0)
112			odata = 0;
113			}
114			debug("[ rd94: intstat1 ]\n");
115			/* cpu_interrupt_ack(cpu, 3); */
116			break;
117	dpavlin	22
118	dpavlin	4	case RD94_SYS_INTSTAT2: /* PCI/EISA */
119			if (writeflag == MEM_WRITE) {
120			} else {
121			odata = 0; /* TODO */
122			}
123			debug("[ rd94: intstat2 ]\n");
124			/* cpu_interrupt_ack(cpu, 4); */
125			break;
126	dpavlin	22
127	dpavlin	4	case RD94_SYS_INTSTAT3: /* IT (Interval Timer) */
128			if (writeflag == MEM_WRITE) {
129			} else {
130			odata = 0; /* return value does not matter? */
131			}
132			debug("[ rd94: intstat3 ]\n");
133			cpu_interrupt_ack(cpu, 5);
134			d->interval = d->interval_start;
135			break;
136	dpavlin	22
137	dpavlin	4	case RD94_SYS_INTSTAT4: /* IPI */
138			if (writeflag == MEM_WRITE) {
139			} else {
140			odata = 0; /* return value does not matter? */
141			}
142			fatal("[ rd94: intstat4 ]\n");
143			cpu_interrupt_ack(cpu, 6);
144			break;
145	dpavlin	22
146	dpavlin	4	case RD94_SYS_CPUID:
147			if (writeflag == MEM_WRITE) {
148			fatal("[ rd94: write to CPUID: 0x%llx ]\n",
149			(long long)idata);
150			} else {
151			odata = cpu->cpu_id;
152			fatal("[ rd94: read from CPUID: 0x%llx ]\n",
153			(long long)odata);
154			}
155			break;
156	dpavlin	22
157	dpavlin	4	case RD94_SYS_EXT_IMASK:
158			if (writeflag == MEM_WRITE) {
159			d->intmask = idata;
160			} else {
161			odata = d->intmask;
162			}
163			break;
164	dpavlin	22
165	dpavlin	4	case RD94_SYS_IT_VALUE:
166			if (writeflag == MEM_WRITE) {
167			d->interval = d->interval_start = idata;
168			debug("[ rd94: setting Interval Timer value to %i ]\n",
169			(int)idata);
170			} else {
171			odata = d->interval_start;
172			/* TODO: or d->interval ? */;
173			}
174			break;
175	dpavlin	22
176	dpavlin	4	case RD94_SYS_PCI_CONFADDR:
177	dpavlin	22	bus_pci_decompose_1(idata, &bus, &dev, &func, &pcireg);
178			bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, pcireg);
179			break;
180
181	dpavlin	4	case RD94_SYS_PCI_CONFDATA:
182	dpavlin	22	bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
183			&odata : &idata, len, writeflag);
184	dpavlin	4	break;
185	dpavlin	22
186			default:if (writeflag == MEM_WRITE) {
187	dpavlin	4	fatal("[ rd94: unimplemented write to address 0x%x, "
188			"data=0x%02x ]\n", (int)relative_addr, (int)idata);
189			} else {
190			fatal("[ rd94: unimplemented read from address 0x%x"
191			" ]\n", (int)relative_addr);
192			}
193			}
194
195			if (writeflag == MEM_READ)
196			memory_writemax64(cpu, data, len, odata);
197
198			return 1;
199			}
200
201
202	dpavlin	22	DEVINIT(rd94)
203	dpavlin	4	{
204			struct rd94_data *d = malloc(sizeof(struct rd94_data));
205			if (d == NULL) {
206			fprintf(stderr, "out of memory\n");
207			exit(1);
208			}
209			memset(d, 0, sizeof(struct rd94_data));
210			d->pciirq = devinit->irq_nr;
211	dpavlin	22	d->pci_data = bus_pci_init(devinit->machine, d->pciirq,
212			0,0, 0,0,0, 0,0,0);
213	dpavlin	4
214			memory_device_register(devinit->machine->memory, devinit->name,
215			devinit->addr, DEV_RD94_LENGTH,
216	dpavlin	20	dev_rd94_access, (void *)d, DM_DEFAULT, NULL);
217	dpavlin	4
218			machine_add_tickfunction(devinit->machine, dev_rd94_tick,
219	dpavlin	24	d, RD94_TICK_SHIFT, 0.0);
220	dpavlin	4
221			devinit->return_ptr = d->pci_data;
222
223			return 1;
224			}
225