src/devices/dev_ram.c

/*
 *  Copyright (C) 2004-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_ram.c,v 1.25 2007/06/15 19:57:33 debug Exp $
 *  
 *  COMMENT: A generic RAM (memory) device
 *
 *  Note: This device can also be used to mirror/alias another part of RAM.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/mman.h>

#include "cpu.h"
#include "devices.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"


/*  #define RAM_DEBUG  */

struct ram_data {
        uint64_t        baseaddress;

        int             mode;
        uint64_t        otheraddress;

        /*  If mode = DEV_RAM_MIRROR:  */
        uint64_t        offset;

        /*  If mode = DEV_RAM_RAM:  */
        unsigned char   *data;
        uint64_t        length;
};


DEVICE_ACCESS(ram)
{
        struct ram_data *d = extra;

#ifdef RAM_DEBUG
        if (writeflag==MEM_READ) {
                debug("[ ram: read from 0x%x, len=%i ]\n",
                    (int)relative_addr, (int)len);
        } else {
                int i;
                debug("[ ram: write to 0x%x:", (int)relative_addr);
                for (i=0; i<len; i++)
                        debug(" %02x", data[i]);
                debug(" (len=%i) ]\n", len);
        }
#endif

        switch (d->mode) {

        case DEV_RAM_MIRROR:
                /*  TODO:  how about caches?  */
                return cpu->memory_rw(cpu, mem,
                    d->otheraddress + relative_addr, data, len,
                    writeflag, PHYSICAL);

        case DEV_RAM_RAM:
                if (writeflag == MEM_WRITE) {
                        memcpy(&d->data[relative_addr], data, len);

                        /*  Invalidate any code translations on a write:  */
                        if (cpu->invalidate_code_translation != NULL) {
                                cpu->invalidate_code_translation(
                                    cpu, d->baseaddress + relative_addr,
                                    INVALIDATE_PADDR);
                        }
                } else {
                        memcpy(data, &d->data[relative_addr], len);
                }
                break;

        default:
                fatal("dev_ram_access(): unknown mode %i\n", d->mode);
                exit(1);
        }

        return 1;
}


/*
 *  dev_ram_init():
 *
 *  Initializes a RAM or mirror device. Things get a bit complicated because
 *  of dyntrans (i.e. mirrored memory ranges should be entered into the
 *  translation arrays just as normal memory and other devices are).
 */
void dev_ram_init(struct machine *machine, uint64_t baseaddr, uint64_t length,
        int mode, uint64_t otheraddress)
{
        struct ram_data *d;
        int flags = DM_DEFAULT, points_to_ram = 1;

        CHECK_ALLOCATION(d = malloc(sizeof(struct ram_data)));
        memset(d, 0, sizeof(struct ram_data));

        if (mode & DEV_RAM_MIGHT_POINT_TO_DEVICES) {
                mode &= ~DEV_RAM_MIGHT_POINT_TO_DEVICES;
                points_to_ram = 0;
        }

        d->mode         = mode;
        d->baseaddress  = baseaddr;
        d->otheraddress = otheraddress;

        switch (d->mode) {

        case DEV_RAM_MIRROR:
                /*
                 *  Calculate the amount that the mirror memory is offset from
                 *  the real (physical) memory. This is used in src/memory_rw.c
                 *  with dyntrans accesses if DM_EMULATED_RAM is set.
                 */
                d->offset = baseaddr - otheraddress;

                /*  Aligned RAM? Then it works with dyntrans.  */
                if (points_to_ram &&
                    (baseaddr & (machine->arch_pagesize-1)) == 0 &&
                    (otheraddress & (machine->arch_pagesize - 1)) == 0 &&
                    (length & (machine->arch_pagesize - 1)) == 0)
                        flags |= DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK
                            | DM_EMULATED_RAM;

                memory_device_register(machine->memory, "ram [mirror]",
                    baseaddr, length, dev_ram_access, d, flags
                    | DM_READS_HAVE_NO_SIDE_EFFECTS, (void *) &d->offset);
                break;

        case DEV_RAM_RAM:
                /*
                 *  Allocate zero-filled RAM using mmap(). If mmap() failed,
                 *  try malloc(), but then memset() must also be called, which
                 *  can be slow for large chunks of memory.
                 */
                d->length = length;
                d->data = (unsigned char *) mmap(NULL, length,
                    PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
                if (d->data == NULL) {
                        CHECK_ALLOCATION(d->data = malloc(length));
                        memset(d->data, 0, length);
                }

                /*  Aligned memory? Then it works with dyntrans.  */
                if ((baseaddr & (machine->arch_pagesize - 1)) == 0 &&
                    (length & (machine->arch_pagesize - 1)) == 0)
                        flags |= DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK;

                memory_device_register(machine->memory, "ram", baseaddr,
                    d->length, dev_ram_access, d, flags
                    | DM_READS_HAVE_NO_SIDE_EFFECTS, d->data);
                break;

        default:
                fatal("dev_ram_access(): unknown mode %i\n", d->mode);
                exit(1);
        }
}

1	/*
2	* Copyright (C) 2004-2007 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: dev_ram.c,v 1.25 2007/06/15 19:57:33 debug Exp $
29	*
30	* COMMENT: A generic RAM (memory) device
31	*
32	* Note: This device can also be used to mirror/alias another part of RAM.
33	*/
34
35	#include <stdio.h>
36	#include <stdlib.h>
37	#include <string.h>
38	#include <sys/types.h>
39	#include <sys/mman.h>
40
41	#include "cpu.h"
42	#include "devices.h"
43	#include "machine.h"
44	#include "memory.h"
45	#include "misc.h"
46
47
48	/* #define RAM_DEBUG */
49
50	struct ram_data {
51	uint64_t baseaddress;
52
53	int mode;
54	uint64_t otheraddress;
55
56	/* If mode = DEV_RAM_MIRROR: */
57	uint64_t offset;
58
59	/* If mode = DEV_RAM_RAM: */
60	unsigned char *data;
61	uint64_t length;
62	};
63
64
65	DEVICE_ACCESS(ram)
66	{
67	struct ram_data *d = extra;
68
69	#ifdef RAM_DEBUG
70	if (writeflag==MEM_READ) {
71	debug("[ ram: read from 0x%x, len=%i ]\n",
72	(int)relative_addr, (int)len);
73	} else {
74	int i;
75	debug("[ ram: write to 0x%x:", (int)relative_addr);
76	for (i=0; i<len; i++)
77	debug(" %02x", data[i]);
78	debug(" (len=%i) ]\n", len);
79	}
80	#endif
81
82	switch (d->mode) {
83
84	case DEV_RAM_MIRROR:
85	/* TODO: how about caches? */
86	return cpu->memory_rw(cpu, mem,
87	d->otheraddress + relative_addr, data, len,
88	writeflag, PHYSICAL);
89
90	case DEV_RAM_RAM:
91	if (writeflag == MEM_WRITE) {
92	memcpy(&d->data[relative_addr], data, len);
93
94	/* Invalidate any code translations on a write: */
95	if (cpu->invalidate_code_translation != NULL) {
96	cpu->invalidate_code_translation(
97	cpu, d->baseaddress + relative_addr,
98	INVALIDATE_PADDR);
99	}
100	} else {
101	memcpy(data, &d->data[relative_addr], len);
102	}
103	break;
104
105	default:
106	fatal("dev_ram_access(): unknown mode %i\n", d->mode);
107	exit(1);
108	}
109
110	return 1;
111	}
112
113
114	/*
115	* dev_ram_init():
116	*
117	* Initializes a RAM or mirror device. Things get a bit complicated because
118	* of dyntrans (i.e. mirrored memory ranges should be entered into the
119	* translation arrays just as normal memory and other devices are).
120	*/
121	void dev_ram_init(struct machine *machine, uint64_t baseaddr, uint64_t length,
122	int mode, uint64_t otheraddress)
123	{
124	struct ram_data *d;
125	int flags = DM_DEFAULT, points_to_ram = 1;
126
127	CHECK_ALLOCATION(d = malloc(sizeof(struct ram_data)));
128	memset(d, 0, sizeof(struct ram_data));
129
130	if (mode & DEV_RAM_MIGHT_POINT_TO_DEVICES) {
131	mode &= ~DEV_RAM_MIGHT_POINT_TO_DEVICES;
132	points_to_ram = 0;
133	}
134
135	d->mode = mode;
136	d->baseaddress = baseaddr;
137	d->otheraddress = otheraddress;
138
139	switch (d->mode) {
140
141	case DEV_RAM_MIRROR:
142	/*
143	* Calculate the amount that the mirror memory is offset from
144	* the real (physical) memory. This is used in src/memory_rw.c
145	* with dyntrans accesses if DM_EMULATED_RAM is set.
146	*/
147	d->offset = baseaddr - otheraddress;
148
149	/* Aligned RAM? Then it works with dyntrans. */
150	if (points_to_ram &&
151	(baseaddr & (machine->arch_pagesize-1)) == 0 &&
152	(otheraddress & (machine->arch_pagesize - 1)) == 0 &&
153	(length & (machine->arch_pagesize - 1)) == 0)
154	flags \|= DM_DYNTRANS_OK \| DM_DYNTRANS_WRITE_OK
155	\| DM_EMULATED_RAM;
156
157	memory_device_register(machine->memory, "ram [mirror]",
158	baseaddr, length, dev_ram_access, d, flags
159	\| DM_READS_HAVE_NO_SIDE_EFFECTS, (void *) &d->offset);
160	break;
161
162	case DEV_RAM_RAM:
163	/*
164	* Allocate zero-filled RAM using mmap(). If mmap() failed,
165	* try malloc(), but then memset() must also be called, which
166	* can be slow for large chunks of memory.
167	*/
168	d->length = length;
169	d->data = (unsigned char *) mmap(NULL, length,
170	PROT_READ \| PROT_WRITE, MAP_ANON \| MAP_PRIVATE, -1, 0);
171	if (d->data == NULL) {
172	CHECK_ALLOCATION(d->data = malloc(length));
173	memset(d->data, 0, length);
174	}
175
176	/* Aligned memory? Then it works with dyntrans. */
177	if ((baseaddr & (machine->arch_pagesize - 1)) == 0 &&
178	(length & (machine->arch_pagesize - 1)) == 0)
179	flags \|= DM_DYNTRANS_OK \| DM_DYNTRANS_WRITE_OK;
180
181	memory_device_register(machine->memory, "ram", baseaddr,
182	d->length, dev_ram_access, d, flags
183	\| DM_READS_HAVE_NO_SIDE_EFFECTS, d->data);
184	break;
185
186	default:
187	fatal("dev_ram_access(): unknown mode %i\n", d->mode);
188	exit(1);
189	}
190	}
191