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/* |
/* |
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* Copyright (C) 2004-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2004-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_ram.c,v 1.20 2005/11/13 00:14:09 debug Exp $ |
* $Id: dev_ram.c,v 1.21 2006/01/01 13:17:17 debug Exp $ |
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* |
* |
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* A generic RAM (memory) device. Can also be used to mirror/alias another |
* A generic RAM (memory) device. Can also be used to mirror/alias another |
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* part of RAM. |
* part of RAM. |
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/* |
/* |
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* dev_ram_access(): |
* dev_ram_access(): |
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*/ |
*/ |
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int dev_ram_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(ram) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
{ |
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struct ram_data *d = extra; |
struct ram_data *d = extra; |
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