/[gxemul]/trunk/src/devices/dev_ps2_stuff.c
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Contents of /trunk/src/devices/dev_ps2_stuff.c

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Revision 18 - (show annotations)
Mon Oct 8 16:19:11 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 9944 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1004 2005/10/27 14:01:10 debug Exp $
20051011        Passing -A as the default boot arg for CATS (works fine with
                OpenBSD/cats).
20051012	Fixing the VGA cursor offset bug, and speeding up framebuffer
		redraws if character cells contain the same thing as during
		the last redraw.
20051013	Adding a slow strd ARM instruction hack.
20051017	Minor updates: Adding a dummy i80321 Verde controller (for
		XScale emulation), fixing the disassembly of the ARM "ldrd"
		instruction, adding "support" for less-than-4KB pages for ARM
		(by not adding them to translation tables).
20051020	Continuing on some HPCarm stuff. A NetBSD/hpcarm kernel prints
		some boot messages on an emulated Jornada 720.
		Making dev_ram work better with dyntrans (speeds up some things
		quite a bit).
20051021	Automatically generating some of the most common ARM load/store
		multiple instructions.
20051022	Better statistics gathering for the ARM load/store multiple.
		Various other dyntrans and device updates.
20051023	Various minor updates.
20051024	Continuing; minor device and dyntrans fine-tuning. Adding the
		first "reasonable" instruction combination hacks for ARM (the
		cores of NetBSD/cats' memset and memcpy).
20051025	Fixing a dyntrans-related bug in dev_vga. Also changing the
		dyntrans low/high access notification to only be updated on
		writes, not reads. Hopefully it will be enough. (dev_vga in
		charcell mode now seems to work correctly with both reads and
		writes.)
		Experimenting with gathering dyntrans statistics (which parts
		of emulated RAM that are actually executed), and adding
		instruction combination hacks for cache cleaning and a part of
		NetBSD's scanc() function.
20051026	Adding a bitmap for ARM emulation which indicates if a page is
		(specifically) user accessible; loads and stores with the t-
		flag set can now use the translation arrays, which results in
		a measurable speedup.
20051027	Dyntrans updates; adding an extra bitmap array for 32-bit
		emulation modes, speeding up the check whether a physical page
		has any code translations or not (O(n) -> O(1)). Doing a
		similar reduction of O(n) to O(1) by avoiding the scan through
		the translation entries on a translation update (32-bit mode
		only).
		Various other minor hacks.
20051029	Quick release, without any testing at all.

==============  RELEASE 0.3.6.2  ==============


1 /*
2 * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_ps2_stuff.c,v 1.24 2005/10/26 14:37:04 debug Exp $
29 *
30 * Playstation 2 misc. stuff:
31 *
32 * offset 0x0000 timer control
33 * offset 0x8000 DMA controller
34 * offset 0xf000 Interrupt register
35 */
36
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <string.h>
40
41 #include "cpu.h"
42 #include "devices.h"
43 #include "machine.h"
44 #include "memory.h"
45 #include "misc.h"
46
47 #include "ee_timerreg.h"
48 #include "ps2_dmacreg.h"
49
50 #define TICK_STEPS_SHIFT 14
51
52 /* NOTE/TODO: This should be the same as in ps2_gs: */
53 #define DEV_PS2_GIF_FAKE_BASE 0x50000000
54
55
56 /*
57 * dev_ps2_stuff_tick():
58 */
59 void dev_ps2_stuff_tick(struct cpu *cpu, void *extra)
60 {
61 struct ps2_data *d = extra;
62 int i;
63
64 /*
65 * Right now this interrupts every now and then.
66 * The main interrupt in NetBSD should be 100 Hz. TODO.
67 */
68 for (i=0; i<N_PS2_TIMERS; i++) {
69 /* Count-up Enable: TODO: by how much? */
70 if (d->timer_mode[i] & T_MODE_CUE)
71 d->timer_count[i] ++;
72
73 if (d->timer_mode[i] & (T_MODE_CMPE | T_MODE_OVFE)) {
74 /* Zero return: */
75 if (d->timer_mode[i] & T_MODE_ZRET)
76 d->timer_count[i] = 0;
77
78 /* irq 9 is timer0, etc. */
79 cpu_interrupt(cpu, 8 + 9 + i);
80
81 /* timer 1..3 are "single-shot"? TODO */
82 if (i > 0)
83 d->timer_mode[i] &= ~(T_MODE_CMPE | T_MODE_OVFF);
84 }
85 }
86 }
87
88
89 /*
90 * dev_ps2_stuff_access():
91 */
92 int dev_ps2_stuff_access(struct cpu *cpu, struct memory *mem,
93 uint64_t relative_addr, unsigned char *data, size_t len,
94 int writeflag, void *extra)
95 {
96 uint64_t idata = 0, odata = 0;
97 int regnr = 0;
98 struct ps2_data *d = extra;
99 int timer_nr = 0;
100
101 if (writeflag == MEM_WRITE)
102 idata = memory_readmax64(cpu, data, len);
103
104 if (relative_addr >= 0x8000 && relative_addr < 0x8000 + DMAC_REGSIZE) {
105 regnr = (relative_addr - 0x8000) / 16;
106 if (writeflag == MEM_READ)
107 odata = d->dmac_reg[regnr];
108 else
109 d->dmac_reg[regnr] = idata;
110 }
111
112 /*
113 * Timer control:
114 * The four timers are at offsets 0, 0x800, 0x1000, and 0x1800.
115 */
116 if (relative_addr < TIMER_REGSIZE) {
117 /* 0, 1, 2, or 3 */
118 timer_nr = (relative_addr & 0x1800) >> 11;
119 relative_addr &= (TIMER_OFS-1);
120 }
121
122 switch (relative_addr) {
123 case 0x0000: /* timer count */
124 if (writeflag == MEM_READ) {
125 odata = d->timer_count[timer_nr];
126 if (timer_nr == 0) {
127 /* :-) TODO: remove this? */
128 d->timer_count[timer_nr] ++;
129 }
130 debug("[ ps2_stuff: read timer %i count: 0x%llx ]\n",
131 timer_nr, (long long)odata);
132 } else {
133 d->timer_count[timer_nr] = idata;
134 debug("[ ps2_stuff: write timer %i count: 0x%llx ]\n",
135 timer_nr, (long long)idata);
136 }
137 break;
138 case 0x0010: /* timer mode */
139 if (writeflag == MEM_READ) {
140 odata = d->timer_mode[timer_nr];
141 debug("[ ps2_stuff: read timer %i mode: 0x%llx ]\n",
142 timer_nr, (long long)odata);
143 } else {
144 d->timer_mode[timer_nr] = idata;
145 debug("[ ps2_stuff: write timer %i mode: 0x%llx ]\n",
146 timer_nr, (long long)idata);
147 }
148 break;
149 case 0x0020: /* timer comp */
150 if (writeflag == MEM_READ) {
151 odata = d->timer_comp[timer_nr];
152 debug("[ ps2_stuff: read timer %i comp: 0x%llx ]\n",
153 timer_nr, (long long)odata);
154 } else {
155 d->timer_comp[timer_nr] = idata;
156 debug("[ ps2_stuff: write timer %i comp: 0x%llx ]\n",
157 timer_nr, (long long)idata);
158 }
159 break;
160 case 0x0030: /* timer hold */
161 if (writeflag == MEM_READ) {
162 odata = d->timer_hold[timer_nr];
163 debug("[ ps2_stuff: read timer %i hold: 0x%llx ]\n",
164 timer_nr, (long long)odata);
165 if (timer_nr >= 2)
166 fatal("[ WARNING: ps2_stuff: read from non-"
167 "existant timer %i hold register ]\n");
168 } else {
169 d->timer_hold[timer_nr] = idata;
170 debug("[ ps2_stuff: write timer %i hold: 0x%llx ]\n",
171 timer_nr, (long long)idata);
172 if (timer_nr >= 2)
173 fatal("[ WARNING: ps2_stuff: write to "
174 "non-existant timer %i hold register ]\n",
175 timer_nr);
176 }
177 break;
178
179 case 0x8000 + D2_CHCR_REG:
180 if (writeflag==MEM_READ) {
181 odata = d->dmac_reg[regnr];
182 /* debug("[ ps2_stuff: dmac read from D2_CHCR "
183 "(0x%llx) ]\n", (long long)d->dmac_reg[regnr]); */
184 } else {
185 /* debug("[ ps2_stuff: dmac write to D2_CHCR, "
186 "data 0x%016llx ]\n", (long long) idata); */
187 if (idata & D_CHCR_STR) {
188 int length = d->dmac_reg[D2_QWC_REG/0x10] * 16;
189 uint64_t from_addr = d->dmac_reg[
190 D2_MADR_REG/0x10];
191 uint64_t to_addr = d->dmac_reg[
192 D2_TADR_REG/0x10];
193 unsigned char *copy_buf;
194
195 debug("[ ps2_stuff: dmac [ch2] transfer addr="
196 "0x%016llx len=0x%lx ]\n", (long long)
197 d->dmac_reg[D2_MADR_REG/0x10],
198 (long)length);
199
200 copy_buf = malloc(length);
201 if (copy_buf == NULL) {
202 fprintf(stderr, "out of memory in "
203 "dev_ps2_stuff_access()\n");
204 exit(1);
205 }
206 cpu->memory_rw(cpu, cpu->mem, from_addr,
207 copy_buf, length, MEM_READ,
208 CACHE_NONE | PHYSICAL);
209 cpu->memory_rw(cpu, cpu->mem,
210 d->other_memory_base[DMA_CH_GIF] + to_addr,
211 copy_buf, length, MEM_WRITE,
212 CACHE_NONE | PHYSICAL);
213 free(copy_buf);
214
215 /* Done with the transfer: */
216 d->dmac_reg[D2_QWC_REG/0x10] = 0;
217 idata &= ~D_CHCR_STR;
218
219 /* interrupt DMA channel 2 */
220 cpu_interrupt(cpu, 8 + 16 + 2);
221 } else
222 debug("[ ps2_stuff: dmac [ch2] stopping "
223 "transfer ]\n");
224 d->dmac_reg[regnr] = idata;
225 return 1;
226 }
227 break;
228
229 case 0x8000 + D2_QWC_REG:
230 case 0x8000 + D2_MADR_REG:
231 case 0x8000 + D2_TADR_REG:
232 /* no debug output */
233 break;
234
235 case 0xe010: /* dmac interrupt status (and mask, */
236 /* the upper 16 bits) */
237 if (writeflag == MEM_WRITE) {
238 uint32_t oldmask = d->dmac_reg[regnr] & 0xffff0000;
239 /* Clear out those bits that are set in idata: */
240 d->dmac_reg[regnr] &= ~idata;
241 d->dmac_reg[regnr] &= 0xffff;
242 d->dmac_reg[regnr] |= oldmask;
243 if (((d->dmac_reg[regnr] & 0xffff) &
244 ((d->dmac_reg[regnr]>>16) & 0xffff)) == 0) {
245 /* irq 3 is the DMAC */
246 cpu_interrupt_ack(cpu, 3);
247 }
248 } else {
249 /* Hm... make it seem like the mask bits are (at
250 least as much as) the interrupt assertions: */
251 odata = d->dmac_reg[regnr];
252 odata |= (odata << 16);
253 }
254 break;
255
256 case 0xf000: /* interrupt register */
257 if (writeflag == MEM_READ) {
258 odata = d->intr;
259 debug("[ ps2_stuff: read from Interrupt Register:"
260 " 0x%llx ]\n", (long long)odata);
261
262 /* TODO: This is _NOT_ correct behavior: */
263 d->intr = 0;
264 cpu_interrupt_ack(cpu, 2);
265 } else {
266 debug("[ ps2_stuff: write to Interrupt Register: "
267 "0x%llx ]\n", (long long)idata);
268 /* Clear out bits that are set in idata: */
269 d->intr &= ~idata;
270
271 if ((d->intr & d->imask) == 0)
272 cpu_interrupt_ack(cpu, 2);
273 }
274 break;
275
276 case 0xf010: /* interrupt mask */
277 if (writeflag == MEM_READ) {
278 odata = d->imask;
279 /* debug("[ ps2_stuff: read from Interrupt Mask "
280 "Register: 0x%llx ]\n", (long long)odata); */
281 } else {
282 /* debug("[ ps2_stuff: write to Interrupt Mask "
283 "Register: 0x%llx ]\n", (long long)idata); */
284 d->imask = idata;
285 }
286 break;
287
288 case 0xf230: /* sbus interrupt register? */
289 if (writeflag == MEM_READ) {
290 odata = d->sbus_smflg;
291 debug("[ ps2_stuff: read from SBUS SMFLG:"
292 " 0x%llx ]\n", (long long)odata);
293 } else {
294 /* Clear bits on write: */
295 debug("[ ps2_stuff: write to SBUS SMFLG:"
296 " 0x%llx ]\n", (long long)idata);
297 d->sbus_smflg &= ~idata;
298 /* irq 1 is SBUS */
299 if (d->sbus_smflg == 0)
300 cpu_interrupt_ack(cpu, 8 + 1);
301 }
302 break;
303 default:
304 if (writeflag==MEM_READ) {
305 debug("[ ps2_stuff: read from addr 0x%x: 0x%llx ]\n",
306 (int)relative_addr, (long long)odata);
307 } else {
308 debug("[ ps2_stuff: write to addr 0x%x: 0x%llx ]\n",
309 (int)relative_addr, (long long)idata);
310 }
311 }
312
313 if (writeflag == MEM_READ)
314 memory_writemax64(cpu, data, len, odata);
315
316 return 1;
317 }
318
319
320 /*
321 * dev_ps2_stuff_init():
322 */
323 struct ps2_data *dev_ps2_stuff_init(struct machine *machine,
324 struct memory *mem, uint64_t baseaddr)
325 {
326 struct ps2_data *d;
327
328 d = malloc(sizeof(struct ps2_data));
329 if (d == NULL) {
330 fprintf(stderr, "out of memory\n");
331 exit(1);
332 }
333 memset(d, 0, sizeof(struct ps2_data));
334
335 d->other_memory_base[DMA_CH_GIF] = DEV_PS2_GIF_FAKE_BASE;
336
337 memory_device_register(mem, "ps2_stuff", baseaddr,
338 DEV_PS2_STUFF_LENGTH, dev_ps2_stuff_access, d, MEM_DEFAULT, NULL);
339 machine_add_tickfunction(machine,
340 dev_ps2_stuff_tick, d, TICK_STEPS_SHIFT);
341
342 return d;
343 }
344

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