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dpavlin |
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/* |
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* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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dpavlin |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
44 |
* $Id: dev_ps2_stuff.c,v 1.34 2007/08/29 20:36:49 debug Exp $ |
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dpavlin |
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* |
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dpavlin |
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* COMMENT: PlayStation 2 misc stuff (timer, DMA, interrupts, ...) |
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dpavlin |
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* |
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* offset 0x0000 timer control |
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* offset 0x8000 DMA controller |
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* offset 0xf000 Interrupt register |
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dpavlin |
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* |
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* The 16 normal PS2 interrupts interrupt at MIPS interrupt 2. |
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* The 16 DMA interrupts are connected to MIPS interrupt 3. |
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* |
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* SBUS interrupts go via PS2 interrupt 1. |
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dpavlin |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "cpu.h" |
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dpavlin |
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#include "device.h" |
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dpavlin |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "ee_timerreg.h" |
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#include "ps2_dmacreg.h" |
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#define TICK_STEPS_SHIFT 14 |
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/* NOTE/TODO: This should be the same as in ps2_gs: */ |
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#define DEV_PS2_GIF_FAKE_BASE 0x50000000 |
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dpavlin |
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#define N_PS2_DMA_CHANNELS 10 |
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#define N_PS2_TIMERS 4 |
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dpavlin |
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dpavlin |
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struct ps2_data { |
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uint32_t timer_count[N_PS2_TIMERS]; |
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uint32_t timer_comp[N_PS2_TIMERS]; |
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uint32_t timer_mode[N_PS2_TIMERS]; |
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uint32_t timer_hold[N_PS2_TIMERS]; |
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/* NOTE: only 0 and 1 are valid */ |
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struct interrupt timer_irq[N_PS2_TIMERS]; |
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uint64_t dmac_reg[DMAC_REGSIZE / 0x10]; |
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struct interrupt dmac_irq; /* MIPS irq 3 */ |
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struct interrupt dma_channel2_irq; /* irq path of channel 2 */ |
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uint64_t other_memory_base[N_PS2_DMA_CHANNELS]; |
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uint32_t intr; |
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uint32_t imask; |
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uint32_t sbus_smflg; |
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struct interrupt intr_irq; /* MIPS irq 2 */ |
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struct interrupt sbus_irq; /* PS2 irq 1 */ |
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}; |
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#define DEV_PS2_LENGTH 0x10000 |
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void ps2_intr_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct ps2_data *d = interrupt->extra; |
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d->intr |= (1 << interrupt->line); |
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if (d->intr & d->imask) |
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INTERRUPT_ASSERT(d->intr_irq); |
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} |
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void ps2_intr_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct ps2_data *d = interrupt->extra; |
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d->intr &= ~(1 << interrupt->line); |
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if (!(d->intr & d->imask)) |
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INTERRUPT_DEASSERT(d->intr_irq); |
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} |
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void ps2_dmac_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct ps2_data *d = interrupt->extra; |
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d->dmac_reg[0x601] |= (1 << interrupt->line); |
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/* TODO: DMA interrupt mask? */ |
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if (d->dmac_reg[0x601] & 0xffff) |
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INTERRUPT_ASSERT(d->dmac_irq); |
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} |
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void ps2_dmac_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct ps2_data *d = interrupt->extra; |
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d->dmac_reg[0x601] &= ~(1 << interrupt->line); |
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/* TODO: DMA interrupt mask? */ |
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if (!(d->dmac_reg[0x601] & 0xffff)) |
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INTERRUPT_DEASSERT(d->dmac_irq); |
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} |
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void ps2_sbus_interrupt_assert(struct interrupt *interrupt) |
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{ |
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/* Note: sbus irq 0 = mask 0x100, sbus irq 1 = mask 0x400 */ |
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struct ps2_data *d = interrupt->extra; |
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d->sbus_smflg |= (1 << (8 + interrupt->line * 2)); |
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/* TODO: SBUS interrupt mask? */ |
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if (d->sbus_smflg != 0) |
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INTERRUPT_ASSERT(d->sbus_irq); |
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} |
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void ps2_sbus_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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/* Note: sbus irq 0 = mask 0x100, sbus irq 1 = mask 0x400 */ |
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struct ps2_data *d = interrupt->extra; |
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d->sbus_smflg &= ~(1 << (8 + interrupt->line * 2)); |
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/* TODO: SBUS interrupt mask? */ |
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if (d->sbus_smflg == 0) |
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INTERRUPT_DEASSERT(d->sbus_irq); |
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} |
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DEVICE_TICK(ps2) |
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{ |
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dpavlin |
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struct ps2_data *d = extra; |
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int i; |
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/* |
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* Right now this interrupts every now and then. |
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* The main interrupt in NetBSD should be 100 Hz. TODO. |
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*/ |
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for (i=0; i<N_PS2_TIMERS; i++) { |
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/* Count-up Enable: TODO: by how much? */ |
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if (d->timer_mode[i] & T_MODE_CUE) |
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d->timer_count[i] ++; |
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if (d->timer_mode[i] & (T_MODE_CMPE | T_MODE_OVFE)) { |
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/* Zero return: */ |
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if (d->timer_mode[i] & T_MODE_ZRET) |
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d->timer_count[i] = 0; |
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dpavlin |
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INTERRUPT_ASSERT(d->timer_irq[i]); |
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dpavlin |
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/* timer 1..3 are "single-shot"? TODO */ |
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dpavlin |
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if (i > 0) { |
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d->timer_mode[i] &= |
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~(T_MODE_CMPE | T_MODE_OVFF); |
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} |
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dpavlin |
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} |
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} |
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} |
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dpavlin |
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DEVICE_ACCESS(ps2) |
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dpavlin |
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{ |
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uint64_t idata = 0, odata = 0; |
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int regnr = 0; |
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struct ps2_data *d = extra; |
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int timer_nr = 0; |
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dpavlin |
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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dpavlin |
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if (relative_addr >= 0x8000 && relative_addr < 0x8000 + DMAC_REGSIZE) { |
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regnr = (relative_addr - 0x8000) / 16; |
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if (writeflag == MEM_READ) |
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odata = d->dmac_reg[regnr]; |
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else |
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d->dmac_reg[regnr] = idata; |
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} |
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/* |
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* Timer control: |
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* The four timers are at offsets 0, 0x800, 0x1000, and 0x1800. |
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*/ |
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if (relative_addr < TIMER_REGSIZE) { |
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/* 0, 1, 2, or 3 */ |
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timer_nr = (relative_addr & 0x1800) >> 11; |
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relative_addr &= (TIMER_OFS-1); |
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} |
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switch (relative_addr) { |
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case 0x0000: /* timer count */ |
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if (writeflag == MEM_READ) { |
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odata = d->timer_count[timer_nr]; |
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if (timer_nr == 0) { |
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/* :-) TODO: remove this? */ |
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d->timer_count[timer_nr] ++; |
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} |
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dpavlin |
34 |
debug("[ ps2: read timer %i count: 0x%llx ]\n", |
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dpavlin |
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timer_nr, (long long)odata); |
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} else { |
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d->timer_count[timer_nr] = idata; |
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dpavlin |
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debug("[ ps2: write timer %i count: 0x%llx ]\n", |
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dpavlin |
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timer_nr, (long long)idata); |
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} |
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break; |
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case 0x0010: /* timer mode */ |
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if (writeflag == MEM_READ) { |
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odata = d->timer_mode[timer_nr]; |
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dpavlin |
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debug("[ ps2: read timer %i mode: 0x%llx ]\n", |
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dpavlin |
4 |
timer_nr, (long long)odata); |
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} else { |
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d->timer_mode[timer_nr] = idata; |
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dpavlin |
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debug("[ ps2: write timer %i mode: 0x%llx ]\n", |
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dpavlin |
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timer_nr, (long long)idata); |
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} |
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break; |
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case 0x0020: /* timer comp */ |
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if (writeflag == MEM_READ) { |
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odata = d->timer_comp[timer_nr]; |
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dpavlin |
34 |
debug("[ ps2: read timer %i comp: 0x%llx ]\n", |
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dpavlin |
4 |
timer_nr, (long long)odata); |
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} else { |
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d->timer_comp[timer_nr] = idata; |
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dpavlin |
34 |
debug("[ ps2: write timer %i comp: 0x%llx ]\n", |
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dpavlin |
4 |
timer_nr, (long long)idata); |
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} |
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break; |
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case 0x0030: /* timer hold */ |
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if (writeflag == MEM_READ) { |
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odata = d->timer_hold[timer_nr]; |
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dpavlin |
34 |
debug("[ ps2: read timer %i hold: 0x%llx ]\n", |
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dpavlin |
4 |
timer_nr, (long long)odata); |
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if (timer_nr >= 2) |
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dpavlin |
34 |
fatal("[ WARNING: ps2: read from non-" |
| 241 |
dpavlin |
4 |
"existant timer %i hold register ]\n"); |
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} else { |
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d->timer_hold[timer_nr] = idata; |
| 244 |
dpavlin |
34 |
debug("[ ps2: write timer %i hold: 0x%llx ]\n", |
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dpavlin |
4 |
timer_nr, (long long)idata); |
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if (timer_nr >= 2) |
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dpavlin |
34 |
fatal("[ WARNING: ps2: write to " |
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dpavlin |
4 |
"non-existant timer %i hold register ]\n", |
| 249 |
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timer_nr); |
| 250 |
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} |
| 251 |
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break; |
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| 253 |
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case 0x8000 + D2_CHCR_REG: |
| 254 |
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if (writeflag==MEM_READ) { |
| 255 |
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odata = d->dmac_reg[regnr]; |
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dpavlin |
34 |
/* debug("[ ps2: dmac read from D2_CHCR " |
| 257 |
dpavlin |
4 |
"(0x%llx) ]\n", (long long)d->dmac_reg[regnr]); */ |
| 258 |
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} else { |
| 259 |
dpavlin |
34 |
/* debug("[ ps2: dmac write to D2_CHCR, " |
| 260 |
dpavlin |
4 |
"data 0x%016llx ]\n", (long long) idata); */ |
| 261 |
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if (idata & D_CHCR_STR) { |
| 262 |
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int length = d->dmac_reg[D2_QWC_REG/0x10] * 16; |
| 263 |
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uint64_t from_addr = d->dmac_reg[ |
| 264 |
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D2_MADR_REG/0x10]; |
| 265 |
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uint64_t to_addr = d->dmac_reg[ |
| 266 |
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D2_TADR_REG/0x10]; |
| 267 |
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unsigned char *copy_buf; |
| 268 |
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| 269 |
dpavlin |
34 |
debug("[ ps2: dmac [ch2] transfer addr=" |
| 270 |
dpavlin |
4 |
"0x%016llx len=0x%lx ]\n", (long long) |
| 271 |
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d->dmac_reg[D2_MADR_REG/0x10], |
| 272 |
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(long)length); |
| 273 |
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| 274 |
dpavlin |
42 |
CHECK_ALLOCATION(copy_buf = malloc(length)); |
| 275 |
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| 276 |
dpavlin |
4 |
cpu->memory_rw(cpu, cpu->mem, from_addr, |
| 277 |
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copy_buf, length, MEM_READ, |
| 278 |
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CACHE_NONE | PHYSICAL); |
| 279 |
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cpu->memory_rw(cpu, cpu->mem, |
| 280 |
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d->other_memory_base[DMA_CH_GIF] + to_addr, |
| 281 |
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copy_buf, length, MEM_WRITE, |
| 282 |
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CACHE_NONE | PHYSICAL); |
| 283 |
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free(copy_buf); |
| 284 |
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| 285 |
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/* Done with the transfer: */ |
| 286 |
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d->dmac_reg[D2_QWC_REG/0x10] = 0; |
| 287 |
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idata &= ~D_CHCR_STR; |
| 288 |
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| 289 |
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/* interrupt DMA channel 2 */ |
| 290 |
dpavlin |
34 |
INTERRUPT_ASSERT(d->dma_channel2_irq); |
| 291 |
dpavlin |
4 |
} else |
| 292 |
dpavlin |
34 |
debug("[ ps2: dmac [ch2] stopping " |
| 293 |
dpavlin |
4 |
"transfer ]\n"); |
| 294 |
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d->dmac_reg[regnr] = idata; |
| 295 |
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return 1; |
| 296 |
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} |
| 297 |
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break; |
| 298 |
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| 299 |
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case 0x8000 + D2_QWC_REG: |
| 300 |
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case 0x8000 + D2_MADR_REG: |
| 301 |
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case 0x8000 + D2_TADR_REG: |
| 302 |
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/* no debug output */ |
| 303 |
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break; |
| 304 |
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| 305 |
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case 0xe010: /* dmac interrupt status (and mask, */ |
| 306 |
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/* the upper 16 bits) */ |
| 307 |
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if (writeflag == MEM_WRITE) { |
| 308 |
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uint32_t oldmask = d->dmac_reg[regnr] & 0xffff0000; |
| 309 |
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/* Clear out those bits that are set in idata: */ |
| 310 |
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d->dmac_reg[regnr] &= ~idata; |
| 311 |
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d->dmac_reg[regnr] &= 0xffff; |
| 312 |
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d->dmac_reg[regnr] |= oldmask; |
| 313 |
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if (((d->dmac_reg[regnr] & 0xffff) & |
| 314 |
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((d->dmac_reg[regnr]>>16) & 0xffff)) == 0) { |
| 315 |
dpavlin |
34 |
INTERRUPT_DEASSERT(d->dmac_irq); |
| 316 |
dpavlin |
4 |
} |
| 317 |
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} else { |
| 318 |
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/* Hm... make it seem like the mask bits are (at |
| 319 |
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least as much as) the interrupt assertions: */ |
| 320 |
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odata = d->dmac_reg[regnr]; |
| 321 |
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odata |= (odata << 16); |
| 322 |
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} |
| 323 |
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break; |
| 324 |
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| 325 |
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case 0xf000: /* interrupt register */ |
| 326 |
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if (writeflag == MEM_READ) { |
| 327 |
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odata = d->intr; |
| 328 |
dpavlin |
34 |
debug("[ ps2: read from Interrupt Register:" |
| 329 |
dpavlin |
4 |
" 0x%llx ]\n", (long long)odata); |
| 330 |
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| 331 |
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/* TODO: This is _NOT_ correct behavior: */ |
| 332 |
dpavlin |
34 |
// d->intr = 0; |
| 333 |
|
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// INTERRUPT_DEASSERT(d->intr_irq); |
| 334 |
dpavlin |
4 |
} else { |
| 335 |
dpavlin |
34 |
debug("[ ps2: write to Interrupt Register: " |
| 336 |
dpavlin |
4 |
"0x%llx ]\n", (long long)idata); |
| 337 |
|
|
/* Clear out bits that are set in idata: */ |
| 338 |
|
|
d->intr &= ~idata; |
| 339 |
|
|
|
| 340 |
|
|
if ((d->intr & d->imask) == 0) |
| 341 |
dpavlin |
34 |
INTERRUPT_DEASSERT(d->intr_irq); |
| 342 |
dpavlin |
4 |
} |
| 343 |
|
|
break; |
| 344 |
|
|
|
| 345 |
|
|
case 0xf010: /* interrupt mask */ |
| 346 |
|
|
if (writeflag == MEM_READ) { |
| 347 |
|
|
odata = d->imask; |
| 348 |
dpavlin |
34 |
/* debug("[ ps2: read from Interrupt Mask " |
| 349 |
dpavlin |
4 |
"Register: 0x%llx ]\n", (long long)odata); */ |
| 350 |
|
|
} else { |
| 351 |
dpavlin |
34 |
/* debug("[ ps2: write to Interrupt Mask " |
| 352 |
dpavlin |
4 |
"Register: 0x%llx ]\n", (long long)idata); */ |
| 353 |
dpavlin |
34 |
/* Note: written value indicates which bits |
| 354 |
|
|
to _toggle_, not which bits to set! */ |
| 355 |
|
|
d->imask ^= idata; |
| 356 |
dpavlin |
4 |
} |
| 357 |
|
|
break; |
| 358 |
|
|
|
| 359 |
|
|
case 0xf230: /* sbus interrupt register? */ |
| 360 |
|
|
if (writeflag == MEM_READ) { |
| 361 |
|
|
odata = d->sbus_smflg; |
| 362 |
dpavlin |
34 |
debug("[ ps2: read from SBUS SMFLG:" |
| 363 |
dpavlin |
4 |
" 0x%llx ]\n", (long long)odata); |
| 364 |
|
|
} else { |
| 365 |
|
|
/* Clear bits on write: */ |
| 366 |
dpavlin |
34 |
debug("[ ps2: write to SBUS SMFLG:" |
| 367 |
dpavlin |
4 |
" 0x%llx ]\n", (long long)idata); |
| 368 |
|
|
d->sbus_smflg &= ~idata; |
| 369 |
|
|
/* irq 1 is SBUS */ |
| 370 |
|
|
if (d->sbus_smflg == 0) |
| 371 |
dpavlin |
34 |
INTERRUPT_DEASSERT(d->sbus_irq); |
| 372 |
dpavlin |
4 |
} |
| 373 |
|
|
break; |
| 374 |
|
|
default: |
| 375 |
|
|
if (writeflag==MEM_READ) { |
| 376 |
dpavlin |
34 |
debug("[ ps2: read from addr 0x%x: 0x%llx ]\n", |
| 377 |
dpavlin |
4 |
(int)relative_addr, (long long)odata); |
| 378 |
|
|
} else { |
| 379 |
dpavlin |
34 |
debug("[ ps2: write to addr 0x%x: 0x%llx ]\n", |
| 380 |
dpavlin |
4 |
(int)relative_addr, (long long)idata); |
| 381 |
|
|
} |
| 382 |
|
|
} |
| 383 |
|
|
|
| 384 |
|
|
if (writeflag == MEM_READ) |
| 385 |
|
|
memory_writemax64(cpu, data, len, odata); |
| 386 |
|
|
|
| 387 |
|
|
return 1; |
| 388 |
|
|
} |
| 389 |
|
|
|
| 390 |
|
|
|
| 391 |
dpavlin |
34 |
DEVINIT(ps2) |
| 392 |
dpavlin |
4 |
{ |
| 393 |
|
|
struct ps2_data *d; |
| 394 |
dpavlin |
34 |
int i; |
| 395 |
|
|
struct interrupt template; |
| 396 |
|
|
char n[300]; |
| 397 |
dpavlin |
4 |
|
| 398 |
dpavlin |
42 |
CHECK_ALLOCATION(d = malloc(sizeof(struct ps2_data))); |
| 399 |
dpavlin |
4 |
memset(d, 0, sizeof(struct ps2_data)); |
| 400 |
|
|
|
| 401 |
|
|
d->other_memory_base[DMA_CH_GIF] = DEV_PS2_GIF_FAKE_BASE; |
| 402 |
|
|
|
| 403 |
dpavlin |
34 |
/* Connect to MIPS irq 2 (interrupt controller) and 3 (dmac): */ |
| 404 |
|
|
snprintf(n, sizeof(n), "%s.2", devinit->interrupt_path); |
| 405 |
|
|
INTERRUPT_CONNECT(n, d->intr_irq); |
| 406 |
|
|
snprintf(n, sizeof(n), "%s.3", devinit->interrupt_path); |
| 407 |
|
|
INTERRUPT_CONNECT(n, d->dmac_irq); |
| 408 |
dpavlin |
4 |
|
| 409 |
dpavlin |
34 |
/* |
| 410 |
|
|
* Register interrupts: |
| 411 |
|
|
* |
| 412 |
dpavlin |
44 |
* 16 normal IRQs (machine[x].cpu[x].ps2_intr.%i) |
| 413 |
|
|
* 16 DMA IRQs (machine[x].cpu[x].ps2_dmac.%i) |
| 414 |
|
|
* 2 sbus IRQs (machine[x].cpu[x].ps2_sbus.%i) |
| 415 |
dpavlin |
34 |
*/ |
| 416 |
|
|
for (i=0; i<16; i++) { |
| 417 |
|
|
snprintf(n, sizeof(n), "%s.ps2_intr.%i", |
| 418 |
|
|
devinit->interrupt_path, i); |
| 419 |
|
|
memset(&template, 0, sizeof(template)); |
| 420 |
|
|
template.line = i; |
| 421 |
|
|
template.name = n; |
| 422 |
|
|
template.extra = d; |
| 423 |
|
|
template.interrupt_assert = ps2_intr_interrupt_assert; |
| 424 |
|
|
template.interrupt_deassert = ps2_intr_interrupt_deassert; |
| 425 |
|
|
interrupt_handler_register(&template); |
| 426 |
|
|
} |
| 427 |
|
|
for (i=0; i<16; i++) { |
| 428 |
|
|
snprintf(n, sizeof(n), "%s.ps2_dmac.%i", |
| 429 |
|
|
devinit->interrupt_path, i); |
| 430 |
|
|
memset(&template, 0, sizeof(template)); |
| 431 |
|
|
template.line = i; |
| 432 |
|
|
template.name = n; |
| 433 |
|
|
template.extra = d; |
| 434 |
|
|
template.interrupt_assert = ps2_dmac_interrupt_assert; |
| 435 |
|
|
template.interrupt_deassert = ps2_dmac_interrupt_deassert; |
| 436 |
|
|
interrupt_handler_register(&template); |
| 437 |
|
|
} |
| 438 |
|
|
for (i=0; i<2; i++) { |
| 439 |
|
|
snprintf(n, sizeof(n), "%s.ps2_sbus.%i", |
| 440 |
|
|
devinit->interrupt_path, i); |
| 441 |
|
|
memset(&template, 0, sizeof(template)); |
| 442 |
|
|
template.line = i; |
| 443 |
|
|
template.name = n; |
| 444 |
|
|
template.extra = d; |
| 445 |
|
|
template.interrupt_assert = ps2_sbus_interrupt_assert; |
| 446 |
|
|
template.interrupt_deassert = ps2_sbus_interrupt_deassert; |
| 447 |
|
|
interrupt_handler_register(&template); |
| 448 |
|
|
} |
| 449 |
|
|
|
| 450 |
|
|
/* Connect to DMA channel 2 irq: */ |
| 451 |
|
|
snprintf(n, sizeof(n), "%s.ps2_dmac.2", devinit->interrupt_path); |
| 452 |
|
|
INTERRUPT_CONNECT(n, d->dma_channel2_irq); |
| 453 |
|
|
|
| 454 |
|
|
/* Connect to SBUS interrupt, at ps2 interrupt 1: */ |
| 455 |
|
|
snprintf(n, sizeof(n), "%s.ps2_intr.1", devinit->interrupt_path); |
| 456 |
|
|
INTERRUPT_CONNECT(n, d->sbus_irq); |
| 457 |
|
|
|
| 458 |
|
|
/* Connect to the timers' interrupts: */ |
| 459 |
|
|
for (i=0; i<N_PS2_TIMERS; i++) { |
| 460 |
|
|
/* PS2 irq 9 is timer0, etc. */ |
| 461 |
|
|
snprintf(n, sizeof(n), "%s.ps2_intr.%i", |
| 462 |
|
|
devinit->interrupt_path, 9 + i); |
| 463 |
|
|
INTERRUPT_CONNECT(n, d->timer_irq[i]); |
| 464 |
|
|
} |
| 465 |
|
|
|
| 466 |
|
|
memory_device_register(devinit->machine->memory, "ps2", devinit->addr, |
| 467 |
|
|
DEV_PS2_LENGTH, dev_ps2_access, d, DM_DEFAULT, NULL); |
| 468 |
|
|
machine_add_tickfunction(devinit->machine, |
| 469 |
dpavlin |
42 |
dev_ps2_tick, d, TICK_STEPS_SHIFT); |
| 470 |
dpavlin |
34 |
|
| 471 |
|
|
return 1; |
| 472 |
dpavlin |
4 |
} |
| 473 |
|
|
|
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