/[gxemul]/trunk/src/devices/dev_ps2_stuff.c
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Contents of /trunk/src/devices/dev_ps2_stuff.c

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Revision 20 - (show annotations)
Mon Oct 8 16:19:23 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 9943 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============


1 /*
2 * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_ps2_stuff.c,v 1.25 2005/11/13 00:14:09 debug Exp $
29 *
30 * Playstation 2 misc. stuff:
31 *
32 * offset 0x0000 timer control
33 * offset 0x8000 DMA controller
34 * offset 0xf000 Interrupt register
35 */
36
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <string.h>
40
41 #include "cpu.h"
42 #include "devices.h"
43 #include "machine.h"
44 #include "memory.h"
45 #include "misc.h"
46
47 #include "ee_timerreg.h"
48 #include "ps2_dmacreg.h"
49
50 #define TICK_STEPS_SHIFT 14
51
52 /* NOTE/TODO: This should be the same as in ps2_gs: */
53 #define DEV_PS2_GIF_FAKE_BASE 0x50000000
54
55
56 /*
57 * dev_ps2_stuff_tick():
58 */
59 void dev_ps2_stuff_tick(struct cpu *cpu, void *extra)
60 {
61 struct ps2_data *d = extra;
62 int i;
63
64 /*
65 * Right now this interrupts every now and then.
66 * The main interrupt in NetBSD should be 100 Hz. TODO.
67 */
68 for (i=0; i<N_PS2_TIMERS; i++) {
69 /* Count-up Enable: TODO: by how much? */
70 if (d->timer_mode[i] & T_MODE_CUE)
71 d->timer_count[i] ++;
72
73 if (d->timer_mode[i] & (T_MODE_CMPE | T_MODE_OVFE)) {
74 /* Zero return: */
75 if (d->timer_mode[i] & T_MODE_ZRET)
76 d->timer_count[i] = 0;
77
78 /* irq 9 is timer0, etc. */
79 cpu_interrupt(cpu, 8 + 9 + i);
80
81 /* timer 1..3 are "single-shot"? TODO */
82 if (i > 0)
83 d->timer_mode[i] &= ~(T_MODE_CMPE | T_MODE_OVFF);
84 }
85 }
86 }
87
88
89 /*
90 * dev_ps2_stuff_access():
91 */
92 int dev_ps2_stuff_access(struct cpu *cpu, struct memory *mem,
93 uint64_t relative_addr, unsigned char *data, size_t len,
94 int writeflag, void *extra)
95 {
96 uint64_t idata = 0, odata = 0;
97 int regnr = 0;
98 struct ps2_data *d = extra;
99 int timer_nr = 0;
100
101 if (writeflag == MEM_WRITE)
102 idata = memory_readmax64(cpu, data, len);
103
104 if (relative_addr >= 0x8000 && relative_addr < 0x8000 + DMAC_REGSIZE) {
105 regnr = (relative_addr - 0x8000) / 16;
106 if (writeflag == MEM_READ)
107 odata = d->dmac_reg[regnr];
108 else
109 d->dmac_reg[regnr] = idata;
110 }
111
112 /*
113 * Timer control:
114 * The four timers are at offsets 0, 0x800, 0x1000, and 0x1800.
115 */
116 if (relative_addr < TIMER_REGSIZE) {
117 /* 0, 1, 2, or 3 */
118 timer_nr = (relative_addr & 0x1800) >> 11;
119 relative_addr &= (TIMER_OFS-1);
120 }
121
122 switch (relative_addr) {
123 case 0x0000: /* timer count */
124 if (writeflag == MEM_READ) {
125 odata = d->timer_count[timer_nr];
126 if (timer_nr == 0) {
127 /* :-) TODO: remove this? */
128 d->timer_count[timer_nr] ++;
129 }
130 debug("[ ps2_stuff: read timer %i count: 0x%llx ]\n",
131 timer_nr, (long long)odata);
132 } else {
133 d->timer_count[timer_nr] = idata;
134 debug("[ ps2_stuff: write timer %i count: 0x%llx ]\n",
135 timer_nr, (long long)idata);
136 }
137 break;
138 case 0x0010: /* timer mode */
139 if (writeflag == MEM_READ) {
140 odata = d->timer_mode[timer_nr];
141 debug("[ ps2_stuff: read timer %i mode: 0x%llx ]\n",
142 timer_nr, (long long)odata);
143 } else {
144 d->timer_mode[timer_nr] = idata;
145 debug("[ ps2_stuff: write timer %i mode: 0x%llx ]\n",
146 timer_nr, (long long)idata);
147 }
148 break;
149 case 0x0020: /* timer comp */
150 if (writeflag == MEM_READ) {
151 odata = d->timer_comp[timer_nr];
152 debug("[ ps2_stuff: read timer %i comp: 0x%llx ]\n",
153 timer_nr, (long long)odata);
154 } else {
155 d->timer_comp[timer_nr] = idata;
156 debug("[ ps2_stuff: write timer %i comp: 0x%llx ]\n",
157 timer_nr, (long long)idata);
158 }
159 break;
160 case 0x0030: /* timer hold */
161 if (writeflag == MEM_READ) {
162 odata = d->timer_hold[timer_nr];
163 debug("[ ps2_stuff: read timer %i hold: 0x%llx ]\n",
164 timer_nr, (long long)odata);
165 if (timer_nr >= 2)
166 fatal("[ WARNING: ps2_stuff: read from non-"
167 "existant timer %i hold register ]\n");
168 } else {
169 d->timer_hold[timer_nr] = idata;
170 debug("[ ps2_stuff: write timer %i hold: 0x%llx ]\n",
171 timer_nr, (long long)idata);
172 if (timer_nr >= 2)
173 fatal("[ WARNING: ps2_stuff: write to "
174 "non-existant timer %i hold register ]\n",
175 timer_nr);
176 }
177 break;
178
179 case 0x8000 + D2_CHCR_REG:
180 if (writeflag==MEM_READ) {
181 odata = d->dmac_reg[regnr];
182 /* debug("[ ps2_stuff: dmac read from D2_CHCR "
183 "(0x%llx) ]\n", (long long)d->dmac_reg[regnr]); */
184 } else {
185 /* debug("[ ps2_stuff: dmac write to D2_CHCR, "
186 "data 0x%016llx ]\n", (long long) idata); */
187 if (idata & D_CHCR_STR) {
188 int length = d->dmac_reg[D2_QWC_REG/0x10] * 16;
189 uint64_t from_addr = d->dmac_reg[
190 D2_MADR_REG/0x10];
191 uint64_t to_addr = d->dmac_reg[
192 D2_TADR_REG/0x10];
193 unsigned char *copy_buf;
194
195 debug("[ ps2_stuff: dmac [ch2] transfer addr="
196 "0x%016llx len=0x%lx ]\n", (long long)
197 d->dmac_reg[D2_MADR_REG/0x10],
198 (long)length);
199
200 copy_buf = malloc(length);
201 if (copy_buf == NULL) {
202 fprintf(stderr, "out of memory in "
203 "dev_ps2_stuff_access()\n");
204 exit(1);
205 }
206 cpu->memory_rw(cpu, cpu->mem, from_addr,
207 copy_buf, length, MEM_READ,
208 CACHE_NONE | PHYSICAL);
209 cpu->memory_rw(cpu, cpu->mem,
210 d->other_memory_base[DMA_CH_GIF] + to_addr,
211 copy_buf, length, MEM_WRITE,
212 CACHE_NONE | PHYSICAL);
213 free(copy_buf);
214
215 /* Done with the transfer: */
216 d->dmac_reg[D2_QWC_REG/0x10] = 0;
217 idata &= ~D_CHCR_STR;
218
219 /* interrupt DMA channel 2 */
220 cpu_interrupt(cpu, 8 + 16 + 2);
221 } else
222 debug("[ ps2_stuff: dmac [ch2] stopping "
223 "transfer ]\n");
224 d->dmac_reg[regnr] = idata;
225 return 1;
226 }
227 break;
228
229 case 0x8000 + D2_QWC_REG:
230 case 0x8000 + D2_MADR_REG:
231 case 0x8000 + D2_TADR_REG:
232 /* no debug output */
233 break;
234
235 case 0xe010: /* dmac interrupt status (and mask, */
236 /* the upper 16 bits) */
237 if (writeflag == MEM_WRITE) {
238 uint32_t oldmask = d->dmac_reg[regnr] & 0xffff0000;
239 /* Clear out those bits that are set in idata: */
240 d->dmac_reg[regnr] &= ~idata;
241 d->dmac_reg[regnr] &= 0xffff;
242 d->dmac_reg[regnr] |= oldmask;
243 if (((d->dmac_reg[regnr] & 0xffff) &
244 ((d->dmac_reg[regnr]>>16) & 0xffff)) == 0) {
245 /* irq 3 is the DMAC */
246 cpu_interrupt_ack(cpu, 3);
247 }
248 } else {
249 /* Hm... make it seem like the mask bits are (at
250 least as much as) the interrupt assertions: */
251 odata = d->dmac_reg[regnr];
252 odata |= (odata << 16);
253 }
254 break;
255
256 case 0xf000: /* interrupt register */
257 if (writeflag == MEM_READ) {
258 odata = d->intr;
259 debug("[ ps2_stuff: read from Interrupt Register:"
260 " 0x%llx ]\n", (long long)odata);
261
262 /* TODO: This is _NOT_ correct behavior: */
263 d->intr = 0;
264 cpu_interrupt_ack(cpu, 2);
265 } else {
266 debug("[ ps2_stuff: write to Interrupt Register: "
267 "0x%llx ]\n", (long long)idata);
268 /* Clear out bits that are set in idata: */
269 d->intr &= ~idata;
270
271 if ((d->intr & d->imask) == 0)
272 cpu_interrupt_ack(cpu, 2);
273 }
274 break;
275
276 case 0xf010: /* interrupt mask */
277 if (writeflag == MEM_READ) {
278 odata = d->imask;
279 /* debug("[ ps2_stuff: read from Interrupt Mask "
280 "Register: 0x%llx ]\n", (long long)odata); */
281 } else {
282 /* debug("[ ps2_stuff: write to Interrupt Mask "
283 "Register: 0x%llx ]\n", (long long)idata); */
284 d->imask = idata;
285 }
286 break;
287
288 case 0xf230: /* sbus interrupt register? */
289 if (writeflag == MEM_READ) {
290 odata = d->sbus_smflg;
291 debug("[ ps2_stuff: read from SBUS SMFLG:"
292 " 0x%llx ]\n", (long long)odata);
293 } else {
294 /* Clear bits on write: */
295 debug("[ ps2_stuff: write to SBUS SMFLG:"
296 " 0x%llx ]\n", (long long)idata);
297 d->sbus_smflg &= ~idata;
298 /* irq 1 is SBUS */
299 if (d->sbus_smflg == 0)
300 cpu_interrupt_ack(cpu, 8 + 1);
301 }
302 break;
303 default:
304 if (writeflag==MEM_READ) {
305 debug("[ ps2_stuff: read from addr 0x%x: 0x%llx ]\n",
306 (int)relative_addr, (long long)odata);
307 } else {
308 debug("[ ps2_stuff: write to addr 0x%x: 0x%llx ]\n",
309 (int)relative_addr, (long long)idata);
310 }
311 }
312
313 if (writeflag == MEM_READ)
314 memory_writemax64(cpu, data, len, odata);
315
316 return 1;
317 }
318
319
320 /*
321 * dev_ps2_stuff_init():
322 */
323 struct ps2_data *dev_ps2_stuff_init(struct machine *machine,
324 struct memory *mem, uint64_t baseaddr)
325 {
326 struct ps2_data *d;
327
328 d = malloc(sizeof(struct ps2_data));
329 if (d == NULL) {
330 fprintf(stderr, "out of memory\n");
331 exit(1);
332 }
333 memset(d, 0, sizeof(struct ps2_data));
334
335 d->other_memory_base[DMA_CH_GIF] = DEV_PS2_GIF_FAKE_BASE;
336
337 memory_device_register(mem, "ps2_stuff", baseaddr,
338 DEV_PS2_STUFF_LENGTH, dev_ps2_stuff_access, d, DM_DEFAULT, NULL);
339 machine_add_tickfunction(machine,
340 dev_ps2_stuff_tick, d, TICK_STEPS_SHIFT);
341
342 return d;
343 }
344

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