/[gxemul]/trunk/src/devices/dev_ps2_stuff.c
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Annotation of /trunk/src/devices/dev_ps2_stuff.c

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Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 dpavlin 4 /*
2 dpavlin 22 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3 dpavlin 4 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 22 * $Id: dev_ps2_stuff.c,v 1.27 2006/01/01 13:17:17 debug Exp $
29 dpavlin 4 *
30     * Playstation 2 misc. stuff:
31     *
32     * offset 0x0000 timer control
33     * offset 0x8000 DMA controller
34     * offset 0xf000 Interrupt register
35     */
36    
37     #include <stdio.h>
38     #include <stdlib.h>
39     #include <string.h>
40    
41     #include "cpu.h"
42     #include "devices.h"
43     #include "machine.h"
44     #include "memory.h"
45     #include "misc.h"
46    
47     #include "ee_timerreg.h"
48     #include "ps2_dmacreg.h"
49    
50     #define TICK_STEPS_SHIFT 14
51    
52     /* NOTE/TODO: This should be the same as in ps2_gs: */
53     #define DEV_PS2_GIF_FAKE_BASE 0x50000000
54    
55    
56     /*
57     * dev_ps2_stuff_tick():
58     */
59     void dev_ps2_stuff_tick(struct cpu *cpu, void *extra)
60     {
61     struct ps2_data *d = extra;
62     int i;
63    
64     /*
65     * Right now this interrupts every now and then.
66     * The main interrupt in NetBSD should be 100 Hz. TODO.
67     */
68     for (i=0; i<N_PS2_TIMERS; i++) {
69     /* Count-up Enable: TODO: by how much? */
70     if (d->timer_mode[i] & T_MODE_CUE)
71     d->timer_count[i] ++;
72    
73     if (d->timer_mode[i] & (T_MODE_CMPE | T_MODE_OVFE)) {
74     /* Zero return: */
75     if (d->timer_mode[i] & T_MODE_ZRET)
76     d->timer_count[i] = 0;
77    
78     /* irq 9 is timer0, etc. */
79     cpu_interrupt(cpu, 8 + 9 + i);
80    
81     /* timer 1..3 are "single-shot"? TODO */
82 dpavlin 22 if (i > 0) {
83     d->timer_mode[i] &=
84     ~(T_MODE_CMPE | T_MODE_OVFF);
85     }
86 dpavlin 4 }
87     }
88     }
89    
90    
91     /*
92     * dev_ps2_stuff_access():
93     */
94 dpavlin 22 DEVICE_ACCESS(ps2_stuff)
95 dpavlin 4 {
96     uint64_t idata = 0, odata = 0;
97     int regnr = 0;
98     struct ps2_data *d = extra;
99     int timer_nr = 0;
100    
101 dpavlin 18 if (writeflag == MEM_WRITE)
102     idata = memory_readmax64(cpu, data, len);
103 dpavlin 4
104     if (relative_addr >= 0x8000 && relative_addr < 0x8000 + DMAC_REGSIZE) {
105     regnr = (relative_addr - 0x8000) / 16;
106     if (writeflag == MEM_READ)
107     odata = d->dmac_reg[regnr];
108     else
109     d->dmac_reg[regnr] = idata;
110     }
111    
112     /*
113     * Timer control:
114     * The four timers are at offsets 0, 0x800, 0x1000, and 0x1800.
115     */
116     if (relative_addr < TIMER_REGSIZE) {
117     /* 0, 1, 2, or 3 */
118     timer_nr = (relative_addr & 0x1800) >> 11;
119     relative_addr &= (TIMER_OFS-1);
120     }
121    
122     switch (relative_addr) {
123     case 0x0000: /* timer count */
124     if (writeflag == MEM_READ) {
125     odata = d->timer_count[timer_nr];
126     if (timer_nr == 0) {
127     /* :-) TODO: remove this? */
128     d->timer_count[timer_nr] ++;
129     }
130     debug("[ ps2_stuff: read timer %i count: 0x%llx ]\n",
131     timer_nr, (long long)odata);
132     } else {
133     d->timer_count[timer_nr] = idata;
134     debug("[ ps2_stuff: write timer %i count: 0x%llx ]\n",
135     timer_nr, (long long)idata);
136     }
137     break;
138     case 0x0010: /* timer mode */
139     if (writeflag == MEM_READ) {
140     odata = d->timer_mode[timer_nr];
141     debug("[ ps2_stuff: read timer %i mode: 0x%llx ]\n",
142     timer_nr, (long long)odata);
143     } else {
144     d->timer_mode[timer_nr] = idata;
145     debug("[ ps2_stuff: write timer %i mode: 0x%llx ]\n",
146     timer_nr, (long long)idata);
147     }
148     break;
149     case 0x0020: /* timer comp */
150     if (writeflag == MEM_READ) {
151     odata = d->timer_comp[timer_nr];
152     debug("[ ps2_stuff: read timer %i comp: 0x%llx ]\n",
153     timer_nr, (long long)odata);
154     } else {
155     d->timer_comp[timer_nr] = idata;
156     debug("[ ps2_stuff: write timer %i comp: 0x%llx ]\n",
157     timer_nr, (long long)idata);
158     }
159     break;
160     case 0x0030: /* timer hold */
161     if (writeflag == MEM_READ) {
162     odata = d->timer_hold[timer_nr];
163     debug("[ ps2_stuff: read timer %i hold: 0x%llx ]\n",
164     timer_nr, (long long)odata);
165     if (timer_nr >= 2)
166     fatal("[ WARNING: ps2_stuff: read from non-"
167     "existant timer %i hold register ]\n");
168     } else {
169     d->timer_hold[timer_nr] = idata;
170     debug("[ ps2_stuff: write timer %i hold: 0x%llx ]\n",
171     timer_nr, (long long)idata);
172     if (timer_nr >= 2)
173     fatal("[ WARNING: ps2_stuff: write to "
174     "non-existant timer %i hold register ]\n",
175     timer_nr);
176     }
177     break;
178    
179     case 0x8000 + D2_CHCR_REG:
180     if (writeflag==MEM_READ) {
181     odata = d->dmac_reg[regnr];
182     /* debug("[ ps2_stuff: dmac read from D2_CHCR "
183     "(0x%llx) ]\n", (long long)d->dmac_reg[regnr]); */
184     } else {
185     /* debug("[ ps2_stuff: dmac write to D2_CHCR, "
186     "data 0x%016llx ]\n", (long long) idata); */
187     if (idata & D_CHCR_STR) {
188     int length = d->dmac_reg[D2_QWC_REG/0x10] * 16;
189     uint64_t from_addr = d->dmac_reg[
190     D2_MADR_REG/0x10];
191     uint64_t to_addr = d->dmac_reg[
192     D2_TADR_REG/0x10];
193     unsigned char *copy_buf;
194    
195     debug("[ ps2_stuff: dmac [ch2] transfer addr="
196     "0x%016llx len=0x%lx ]\n", (long long)
197     d->dmac_reg[D2_MADR_REG/0x10],
198     (long)length);
199    
200     copy_buf = malloc(length);
201     if (copy_buf == NULL) {
202     fprintf(stderr, "out of memory in "
203     "dev_ps2_stuff_access()\n");
204     exit(1);
205     }
206     cpu->memory_rw(cpu, cpu->mem, from_addr,
207     copy_buf, length, MEM_READ,
208     CACHE_NONE | PHYSICAL);
209     cpu->memory_rw(cpu, cpu->mem,
210     d->other_memory_base[DMA_CH_GIF] + to_addr,
211     copy_buf, length, MEM_WRITE,
212     CACHE_NONE | PHYSICAL);
213     free(copy_buf);
214    
215     /* Done with the transfer: */
216     d->dmac_reg[D2_QWC_REG/0x10] = 0;
217     idata &= ~D_CHCR_STR;
218    
219     /* interrupt DMA channel 2 */
220     cpu_interrupt(cpu, 8 + 16 + 2);
221     } else
222     debug("[ ps2_stuff: dmac [ch2] stopping "
223     "transfer ]\n");
224     d->dmac_reg[regnr] = idata;
225     return 1;
226     }
227     break;
228    
229     case 0x8000 + D2_QWC_REG:
230     case 0x8000 + D2_MADR_REG:
231     case 0x8000 + D2_TADR_REG:
232     /* no debug output */
233     break;
234    
235     case 0xe010: /* dmac interrupt status (and mask, */
236     /* the upper 16 bits) */
237     if (writeflag == MEM_WRITE) {
238     uint32_t oldmask = d->dmac_reg[regnr] & 0xffff0000;
239     /* Clear out those bits that are set in idata: */
240     d->dmac_reg[regnr] &= ~idata;
241     d->dmac_reg[regnr] &= 0xffff;
242     d->dmac_reg[regnr] |= oldmask;
243     if (((d->dmac_reg[regnr] & 0xffff) &
244     ((d->dmac_reg[regnr]>>16) & 0xffff)) == 0) {
245     /* irq 3 is the DMAC */
246     cpu_interrupt_ack(cpu, 3);
247     }
248     } else {
249     /* Hm... make it seem like the mask bits are (at
250     least as much as) the interrupt assertions: */
251     odata = d->dmac_reg[regnr];
252     odata |= (odata << 16);
253     }
254     break;
255    
256     case 0xf000: /* interrupt register */
257     if (writeflag == MEM_READ) {
258     odata = d->intr;
259     debug("[ ps2_stuff: read from Interrupt Register:"
260     " 0x%llx ]\n", (long long)odata);
261    
262     /* TODO: This is _NOT_ correct behavior: */
263     d->intr = 0;
264     cpu_interrupt_ack(cpu, 2);
265     } else {
266     debug("[ ps2_stuff: write to Interrupt Register: "
267     "0x%llx ]\n", (long long)idata);
268     /* Clear out bits that are set in idata: */
269     d->intr &= ~idata;
270    
271     if ((d->intr & d->imask) == 0)
272     cpu_interrupt_ack(cpu, 2);
273     }
274     break;
275    
276     case 0xf010: /* interrupt mask */
277     if (writeflag == MEM_READ) {
278     odata = d->imask;
279     /* debug("[ ps2_stuff: read from Interrupt Mask "
280     "Register: 0x%llx ]\n", (long long)odata); */
281     } else {
282     /* debug("[ ps2_stuff: write to Interrupt Mask "
283     "Register: 0x%llx ]\n", (long long)idata); */
284     d->imask = idata;
285     }
286     break;
287    
288     case 0xf230: /* sbus interrupt register? */
289     if (writeflag == MEM_READ) {
290     odata = d->sbus_smflg;
291     debug("[ ps2_stuff: read from SBUS SMFLG:"
292     " 0x%llx ]\n", (long long)odata);
293     } else {
294     /* Clear bits on write: */
295     debug("[ ps2_stuff: write to SBUS SMFLG:"
296     " 0x%llx ]\n", (long long)idata);
297     d->sbus_smflg &= ~idata;
298     /* irq 1 is SBUS */
299     if (d->sbus_smflg == 0)
300     cpu_interrupt_ack(cpu, 8 + 1);
301     }
302     break;
303     default:
304     if (writeflag==MEM_READ) {
305     debug("[ ps2_stuff: read from addr 0x%x: 0x%llx ]\n",
306     (int)relative_addr, (long long)odata);
307     } else {
308     debug("[ ps2_stuff: write to addr 0x%x: 0x%llx ]\n",
309     (int)relative_addr, (long long)idata);
310     }
311     }
312    
313     if (writeflag == MEM_READ)
314     memory_writemax64(cpu, data, len, odata);
315    
316     return 1;
317     }
318    
319    
320     /*
321     * dev_ps2_stuff_init():
322     */
323     struct ps2_data *dev_ps2_stuff_init(struct machine *machine,
324     struct memory *mem, uint64_t baseaddr)
325     {
326     struct ps2_data *d;
327    
328     d = malloc(sizeof(struct ps2_data));
329     if (d == NULL) {
330     fprintf(stderr, "out of memory\n");
331     exit(1);
332     }
333     memset(d, 0, sizeof(struct ps2_data));
334    
335     d->other_memory_base[DMA_CH_GIF] = DEV_PS2_GIF_FAKE_BASE;
336    
337     memory_device_register(mem, "ps2_stuff", baseaddr,
338 dpavlin 20 DEV_PS2_STUFF_LENGTH, dev_ps2_stuff_access, d, DM_DEFAULT, NULL);
339 dpavlin 4 machine_add_tickfunction(machine,
340     dev_ps2_stuff_tick, d, TICK_STEPS_SHIFT);
341    
342     return d;
343     }
344    

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