/[gxemul]/trunk/src/devices/dev_pccmos.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/devices/dev_pccmos.c

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Revision 28 - (show annotations)
Mon Oct 8 16:20:26 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 5052 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============
1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_pccmos.c,v 1.24 2006/07/11 04:44:09 debug Exp $
29 *
30 * PC CMOS/RTC device (ISA ports 0x70 and 0x71).
31 *
32 * The main point of this device is to be a "PC style wrapper" for accessing
33 * the MC146818 (the RTC). In most other respects, this device is bogus, and
34 * just acts as a 256-byte RAM device.
35 */
36
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <string.h>
40
41 #include "cpu.h"
42 #include "device.h"
43 #include "devices.h"
44 #include "emul.h"
45 #include "machine.h"
46 #include "memory.h"
47 #include "misc.h"
48
49
50 #define DEV_PCCMOS_LENGTH 2
51 #define PCCMOS_MC146818_FAKE_ADDR 0x1d00000000ULL
52
53 struct pccmos_data {
54 unsigned char select;
55 unsigned char ram[256];
56 };
57
58
59 /*
60 * dev_pccmos_access():
61 */
62 DEVICE_ACCESS(pccmos)
63 {
64 struct pccmos_data *d = (struct pccmos_data *) extra;
65 uint64_t idata = 0, odata = 0;
66 unsigned char b = 0;
67 int r = 1;
68
69 if (writeflag == MEM_WRITE)
70 b = idata = memory_readmax64(cpu, data, len);
71
72 /*
73 * Accesses to CMOS register 0 .. 0xd are rerouted to the
74 * RTC; all other access are treated as CMOS RAM read/writes.
75 */
76
77 if ((relative_addr & 1) == 0) {
78 if (writeflag == MEM_WRITE) {
79 d->select = idata;
80 if (idata <= 0x0d) {
81 r = cpu->memory_rw(cpu, cpu->mem,
82 PCCMOS_MC146818_FAKE_ADDR, &b, 1,
83 MEM_WRITE, PHYSICAL);
84 }
85 } else
86 odata = d->select;
87 } else {
88 if (d->select <= 0x0d) {
89 if (writeflag == MEM_WRITE) {
90 r = cpu->memory_rw(cpu, cpu->mem,
91 PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1,
92 MEM_WRITE, PHYSICAL);
93 } else {
94 r = cpu->memory_rw(cpu, cpu->mem,
95 PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1,
96 MEM_READ, PHYSICAL);
97 odata = b;
98 }
99 } else {
100 if (writeflag == MEM_WRITE)
101 d->ram[d->select] = idata;
102 else
103 odata = d->ram[d->select];
104 }
105 }
106
107 if (r == 0)
108 fatal("[ pccmos: memory_rw() error! ]\n");
109
110 if (writeflag == MEM_READ)
111 memory_writemax64(cpu, data, len, odata);
112
113 return 1;
114 }
115
116
117 DEVINIT(pccmos)
118 {
119 struct pccmos_data *d = malloc(sizeof(struct pccmos_data));
120 int irq_nr, type = MC146818_PC_CMOS, len = DEV_PCCMOS_LENGTH;
121
122 if (d == NULL) {
123 fprintf(stderr, "out of memory\n");
124 exit(1);
125 }
126 memset(d, 0, sizeof(struct pccmos_data));
127
128 /*
129 * Different machines use different IRQ schemes.
130 */
131 switch (devinit->machine->machine_type) {
132 case MACHINE_CATS:
133 case MACHINE_NETWINDER:
134 irq_nr = 32 + 8;
135 type = MC146818_CATS;
136 d->ram[0x48] = 20; /* century */
137 len = DEV_PCCMOS_LENGTH * 2;
138 break;
139 case MACHINE_ALGOR:
140 irq_nr = 8 + 8;
141 type = MC146818_ALGOR;
142 break;
143 case MACHINE_ARC:
144 fatal("\nARC pccmos: TODO\n\n");
145 irq_nr = 8 + 8; /* TODO */
146 type = MC146818_ALGOR;
147 break;
148 case MACHINE_EVBMIPS:
149 /* Malta etc. */
150 irq_nr = 8 + 8;
151 type = MC146818_ALGOR;
152 break;
153 case MACHINE_QEMU_MIPS:
154 irq_nr = 8 + 8; /* TODO. Bogus so far. */
155 break;
156 case MACHINE_X86:
157 irq_nr = 16; /* "No" irq */
158 break;
159 case MACHINE_BEBOX:
160 case MACHINE_PREP:
161 case MACHINE_MVMEPPC:
162 irq_nr = 32 + 8;
163 break;
164 case MACHINE_SHARK:
165 case MACHINE_IYONIX:
166 /* TODO */
167 irq_nr = 32 + 8;
168 break;
169 case MACHINE_ALPHA:
170 /* TODO */
171 irq_nr = 32 + 8;
172 break;
173 default:fatal("devinit_pccmos(): unimplemented machine type"
174 " %i\n", devinit->machine->machine_type);
175 exit(1);
176 }
177
178 memory_device_register(devinit->machine->memory, devinit->name,
179 devinit->addr, len, dev_pccmos_access, (void *)d,
180 DM_DEFAULT, NULL);
181
182 dev_mc146818_init(devinit->machine, devinit->machine->memory,
183 PCCMOS_MC146818_FAKE_ADDR, irq_nr, type, 1);
184
185 return 1;
186 }
187
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