25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_pccmos.c,v 1.4 2005/10/04 04:11:14 debug Exp $ |
* $Id: dev_pccmos.c,v 1.7 2005/10/09 22:21:31 debug Exp $ |
29 |
* |
* |
30 |
* PC CMOS/RTC device. |
* PC CMOS/RTC device. |
31 |
* |
* |
74 |
* RTC; all other access are treated as CMOS RAM read/writes. |
* RTC; all other access are treated as CMOS RAM read/writes. |
75 |
*/ |
*/ |
76 |
|
|
77 |
switch (relative_addr) { |
if ((relative_addr & 1) == 0) { |
78 |
case 0: if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
79 |
d->select = idata; |
d->select = idata; |
80 |
if (idata <= 0x0d) { |
if (idata <= 0x0d) { |
81 |
cpu->memory_rw(cpu, cpu->mem, |
cpu->memory_rw(cpu, cpu->mem, |
84 |
} |
} |
85 |
} else |
} else |
86 |
odata = d->select; |
odata = d->select; |
87 |
break; |
} else { |
88 |
case 1: if (d->select <= 0x0d) { |
if (d->select <= 0x0d) { |
89 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
90 |
cpu->memory_rw(cpu, cpu->mem, |
cpu->memory_rw(cpu, cpu->mem, |
91 |
PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1, |
PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1, |
102 |
else |
else |
103 |
odata = d->ram[d->select]; |
odata = d->ram[d->select]; |
104 |
} |
} |
|
break; |
|
|
default: |
|
|
if (writeflag == MEM_WRITE) { |
|
|
fatal("[ pccmos: unimplemented write to address 0x%x" |
|
|
" data=0x%02x ]\n", (int)relative_addr, (int)idata); |
|
|
} else { |
|
|
fatal("[ pccmos: unimplemented read from address 0x%x " |
|
|
"]\n", (int)relative_addr); |
|
|
} |
|
105 |
} |
} |
106 |
|
|
107 |
if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
117 |
int devinit_pccmos(struct devinit *devinit) |
int devinit_pccmos(struct devinit *devinit) |
118 |
{ |
{ |
119 |
struct pccmos_data *d = malloc(sizeof(struct pccmos_data)); |
struct pccmos_data *d = malloc(sizeof(struct pccmos_data)); |
120 |
int irq_nr; |
int irq_nr, type = MC146818_PC_CMOS, len = DEV_PCCMOS_LENGTH; |
121 |
|
|
122 |
if (d == NULL) { |
if (d == NULL) { |
123 |
fprintf(stderr, "out of memory\n"); |
fprintf(stderr, "out of memory\n"); |
125 |
} |
} |
126 |
memset(d, 0, sizeof(struct pccmos_data)); |
memset(d, 0, sizeof(struct pccmos_data)); |
127 |
|
|
|
memory_device_register(devinit->machine->memory, devinit->name, |
|
|
devinit->addr, DEV_PCCMOS_LENGTH, dev_pccmos_access, (void *)d, |
|
|
MEM_DEFAULT, NULL); |
|
|
|
|
128 |
/* |
/* |
129 |
* Different machines use different IRQ schemes. |
* Different machines use different IRQ schemes. |
130 |
*/ |
*/ |
131 |
switch (devinit->machine->machine_type) { |
switch (devinit->machine->machine_type) { |
132 |
case MACHINE_CATS: |
case MACHINE_CATS: |
133 |
irq_nr = 32 + 8; |
irq_nr = 32 + 8; |
134 |
|
type = MC146818_CATS; |
135 |
|
d->ram[0x48] = 20; /* century */ |
136 |
|
len = DEV_PCCMOS_LENGTH * 2; |
137 |
break; |
break; |
138 |
case MACHINE_X86: |
case MACHINE_X86: |
139 |
irq_nr = 16; /* "No" irq */ |
irq_nr = 16; /* "No" irq */ |
143 |
exit(1); |
exit(1); |
144 |
} |
} |
145 |
|
|
146 |
|
memory_device_register(devinit->machine->memory, devinit->name, |
147 |
|
devinit->addr, len, dev_pccmos_access, (void *)d, |
148 |
|
MEM_DEFAULT, NULL); |
149 |
|
|
150 |
dev_mc146818_init(devinit->machine, devinit->machine->memory, |
dev_mc146818_init(devinit->machine, devinit->machine->memory, |
151 |
PCCMOS_MC146818_FAKE_ADDR, irq_nr, MC146818_PC_CMOS, 1); |
PCCMOS_MC146818_FAKE_ADDR, irq_nr, type, 1); |
152 |
|
|
153 |
return 1; |
return 1; |
154 |
} |
} |