25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_pccmos.c,v 1.3 2005/05/20 08:59:58 debug Exp $ |
* $Id: dev_pccmos.c,v 1.4 2005/10/04 04:11:14 debug Exp $ |
29 |
* |
* |
30 |
* PC CMOS/RTC device. |
* PC CMOS/RTC device. |
31 |
* |
* |
32 |
* This is mostly bogus. |
* The main point of this device is to be a "PC style wrapper" for accessing |
33 |
|
* the MC146818 (the RTC). In most other respects, this device is bogus, and |
34 |
|
* just acts as a 256-byte RAM device. |
35 |
*/ |
*/ |
36 |
|
|
37 |
#include <stdio.h> |
#include <stdio.h> |
65 |
{ |
{ |
66 |
struct pccmos_data *d = (struct pccmos_data *) extra; |
struct pccmos_data *d = (struct pccmos_data *) extra; |
67 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
68 |
|
unsigned char b; |
69 |
|
|
70 |
idata = memory_readmax64(cpu, data, len); |
b = idata = memory_readmax64(cpu, data, len); |
71 |
|
|
72 |
|
/* |
73 |
|
* Accesses to CMOS register 0 .. 0xd are rerouted to the |
74 |
|
* RTC; all other access are treated as CMOS RAM read/writes. |
75 |
|
*/ |
76 |
|
|
77 |
switch (relative_addr) { |
switch (relative_addr) { |
78 |
case 0: if (writeflag == MEM_WRITE) { |
case 0: if (writeflag == MEM_WRITE) { |
79 |
d->select = idata; |
d->select = idata; |
80 |
if (idata <= 0x0d) |
if (idata <= 0x0d) { |
81 |
cpu->memory_rw(cpu, cpu->mem, |
cpu->memory_rw(cpu, cpu->mem, |
82 |
PCCMOS_MC146818_FAKE_ADDR, data, 1, |
PCCMOS_MC146818_FAKE_ADDR, &b, 1, |
83 |
MEM_WRITE, PHYSICAL); |
MEM_WRITE, PHYSICAL); |
84 |
|
} |
85 |
} else |
} else |
86 |
odata = d->select; |
odata = d->select; |
87 |
break; |
break; |
88 |
case 1: if (d->select <= 0x0d) { |
case 1: if (d->select <= 0x0d) { |
89 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) { |
90 |
cpu->memory_rw(cpu, cpu->mem, |
cpu->memory_rw(cpu, cpu->mem, |
91 |
PCCMOS_MC146818_FAKE_ADDR + 1, data, 1, |
PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1, |
92 |
MEM_WRITE, PHYSICAL); |
MEM_WRITE, PHYSICAL); |
93 |
else |
} else { |
94 |
cpu->memory_rw(cpu, cpu->mem, |
cpu->memory_rw(cpu, cpu->mem, |
95 |
PCCMOS_MC146818_FAKE_ADDR + 1, data, 1, |
PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1, |
96 |
MEM_READ, PHYSICAL); |
MEM_READ, PHYSICAL); |
97 |
return 1; |
odata = b; |
98 |
|
} |
99 |
} else { |
} else { |
100 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
101 |
d->ram[d->select] = idata; |
d->ram[d->select] = idata; |
126 |
int devinit_pccmos(struct devinit *devinit) |
int devinit_pccmos(struct devinit *devinit) |
127 |
{ |
{ |
128 |
struct pccmos_data *d = malloc(sizeof(struct pccmos_data)); |
struct pccmos_data *d = malloc(sizeof(struct pccmos_data)); |
129 |
|
int irq_nr; |
130 |
|
|
131 |
if (d == NULL) { |
if (d == NULL) { |
132 |
fprintf(stderr, "out of memory\n"); |
fprintf(stderr, "out of memory\n"); |
138 |
devinit->addr, DEV_PCCMOS_LENGTH, dev_pccmos_access, (void *)d, |
devinit->addr, DEV_PCCMOS_LENGTH, dev_pccmos_access, (void *)d, |
139 |
MEM_DEFAULT, NULL); |
MEM_DEFAULT, NULL); |
140 |
|
|
141 |
|
/* |
142 |
|
* Different machines use different IRQ schemes. |
143 |
|
*/ |
144 |
|
switch (devinit->machine->machine_type) { |
145 |
|
case MACHINE_CATS: |
146 |
|
irq_nr = 32 + 8; |
147 |
|
break; |
148 |
|
case MACHINE_X86: |
149 |
|
irq_nr = 16; /* "No" irq */ |
150 |
|
break; |
151 |
|
default:fatal("devinit_pccmos(): unimplemented machine type" |
152 |
|
" %i\n", devinit->machine->machine_type); |
153 |
|
exit(1); |
154 |
|
} |
155 |
|
|
156 |
dev_mc146818_init(devinit->machine, devinit->machine->memory, |
dev_mc146818_init(devinit->machine, devinit->machine->memory, |
157 |
PCCMOS_MC146818_FAKE_ADDR, 16 /* NOTE/TODO: No irq */, |
PCCMOS_MC146818_FAKE_ADDR, irq_nr, MC146818_PC_CMOS, 1); |
|
MC146818_PC_CMOS, 1); |
|
158 |
|
|
159 |
return 1; |
return 1; |
160 |
} |
} |