/[gxemul]/trunk/src/devices/dev_pccmos.c
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Annotation of /trunk/src/devices/dev_pccmos.c

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Revision 22 - (hide annotations)
Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 dpavlin 6 /*
2 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 dpavlin 6 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 22 * $Id: dev_pccmos.c,v 1.22 2006/02/09 20:02:59 debug Exp $
29 dpavlin 6 *
30 dpavlin 22 * PC CMOS/RTC device (ISA ports 0x70 and 0x71).
31 dpavlin 6 *
32 dpavlin 14 * The main point of this device is to be a "PC style wrapper" for accessing
33     * the MC146818 (the RTC). In most other respects, this device is bogus, and
34     * just acts as a 256-byte RAM device.
35 dpavlin 6 */
36    
37     #include <stdio.h>
38     #include <stdlib.h>
39     #include <string.h>
40    
41     #include "cpu.h"
42     #include "device.h"
43     #include "devices.h"
44     #include "emul.h"
45     #include "machine.h"
46     #include "memory.h"
47     #include "misc.h"
48    
49    
50     #define DEV_PCCMOS_LENGTH 2
51     #define PCCMOS_MC146818_FAKE_ADDR 0x1d00000000ULL
52    
53     struct pccmos_data {
54     unsigned char select;
55     unsigned char ram[256];
56     };
57    
58    
59     /*
60     * dev_pccmos_access():
61     */
62 dpavlin 22 DEVICE_ACCESS(pccmos)
63 dpavlin 6 {
64     struct pccmos_data *d = (struct pccmos_data *) extra;
65     uint64_t idata = 0, odata = 0;
66 dpavlin 18 unsigned char b = 0;
67 dpavlin 20 int r = 1;
68 dpavlin 6
69 dpavlin 18 if (writeflag == MEM_WRITE)
70     b = idata = memory_readmax64(cpu, data, len);
71 dpavlin 6
72 dpavlin 14 /*
73     * Accesses to CMOS register 0 .. 0xd are rerouted to the
74     * RTC; all other access are treated as CMOS RAM read/writes.
75     */
76    
77 dpavlin 16 if ((relative_addr & 1) == 0) {
78     if (writeflag == MEM_WRITE) {
79 dpavlin 6 d->select = idata;
80 dpavlin 14 if (idata <= 0x0d) {
81 dpavlin 20 r = cpu->memory_rw(cpu, cpu->mem,
82 dpavlin 14 PCCMOS_MC146818_FAKE_ADDR, &b, 1,
83 dpavlin 6 MEM_WRITE, PHYSICAL);
84 dpavlin 14 }
85 dpavlin 6 } else
86     odata = d->select;
87 dpavlin 16 } else {
88     if (d->select <= 0x0d) {
89 dpavlin 14 if (writeflag == MEM_WRITE) {
90 dpavlin 20 r = cpu->memory_rw(cpu, cpu->mem,
91 dpavlin 14 PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1,
92 dpavlin 6 MEM_WRITE, PHYSICAL);
93 dpavlin 14 } else {
94 dpavlin 20 r = cpu->memory_rw(cpu, cpu->mem,
95 dpavlin 14 PCCMOS_MC146818_FAKE_ADDR + 1, &b, 1,
96 dpavlin 6 MEM_READ, PHYSICAL);
97 dpavlin 14 odata = b;
98     }
99 dpavlin 6 } else {
100     if (writeflag == MEM_WRITE)
101     d->ram[d->select] = idata;
102     else
103     odata = d->ram[d->select];
104     }
105     }
106    
107 dpavlin 20 if (r == 0)
108     fatal("[ pccmos: memory_rw() error! ]\n");
109    
110 dpavlin 6 if (writeflag == MEM_READ)
111     memory_writemax64(cpu, data, len, odata);
112    
113     return 1;
114     }
115    
116    
117 dpavlin 22 DEVINIT(pccmos)
118 dpavlin 6 {
119     struct pccmos_data *d = malloc(sizeof(struct pccmos_data));
120 dpavlin 16 int irq_nr, type = MC146818_PC_CMOS, len = DEV_PCCMOS_LENGTH;
121 dpavlin 6
122     if (d == NULL) {
123     fprintf(stderr, "out of memory\n");
124     exit(1);
125     }
126     memset(d, 0, sizeof(struct pccmos_data));
127    
128 dpavlin 14 /*
129     * Different machines use different IRQ schemes.
130     */
131     switch (devinit->machine->machine_type) {
132     case MACHINE_CATS:
133 dpavlin 20 case MACHINE_NETWINDER:
134 dpavlin 14 irq_nr = 32 + 8;
135 dpavlin 16 type = MC146818_CATS;
136     d->ram[0x48] = 20; /* century */
137     len = DEV_PCCMOS_LENGTH * 2;
138 dpavlin 14 break;
139 dpavlin 20 case MACHINE_ALGOR:
140     irq_nr = 8 + 8;
141     type = MC146818_ALGOR;
142     break;
143 dpavlin 22 case MACHINE_ARC:
144     fatal("\nARC pccmos: TODO\n\n");
145     irq_nr = 8 + 8; /* TODO */
146     type = MC146818_ALGOR;
147     break;
148 dpavlin 20 case MACHINE_EVBMIPS:
149     /* Malta etc. */
150     irq_nr = 8 + 8;
151     type = MC146818_ALGOR;
152     break;
153 dpavlin 14 case MACHINE_X86:
154     irq_nr = 16; /* "No" irq */
155     break;
156 dpavlin 20 case MACHINE_BEBOX:
157     case MACHINE_PREP:
158 dpavlin 22 case MACHINE_MVMEPPC:
159 dpavlin 20 irq_nr = 32 + 8;
160     break;
161 dpavlin 22 case MACHINE_SHARK:
162     case MACHINE_IYONIX:
163     /* TODO */
164     irq_nr = 32 + 8;
165     break;
166 dpavlin 14 default:fatal("devinit_pccmos(): unimplemented machine type"
167     " %i\n", devinit->machine->machine_type);
168     exit(1);
169     }
170    
171 dpavlin 16 memory_device_register(devinit->machine->memory, devinit->name,
172     devinit->addr, len, dev_pccmos_access, (void *)d,
173 dpavlin 20 DM_DEFAULT, NULL);
174 dpavlin 16
175 dpavlin 6 dev_mc146818_init(devinit->machine, devinit->machine->memory,
176 dpavlin 16 PCCMOS_MC146818_FAKE_ADDR, irq_nr, type, 1);
177 dpavlin 6
178     return 1;
179     }
180    

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