src/devices/dev_pcc2.c

/*
 *  Copyright (C) 2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: dev_pcc2.c,v 1.6 2007/08/29 20:36:49 debug Exp $
 *
 *  COMMENT: Peripheral Channel Controller (PCC2) bus (used in MVME machines)
 *
 *  See "Single Board Computers Programmer's Reference Guide (Part 2 of 2)",
 *  "VMESBCA2/PG1" (vmesbcp2.pdf) for more details.
 *
 *  Note: This is somewhat MVME187-specific, at the moment.
 *
 *
 *  TODO: Lots of stuff.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "cpu.h"
#include "device.h"
#include "emul.h"
#include "interrupt.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"


#include "mvme187.h"
#include "mvme_pcctworeg.h"

#define INTERRUPT_LEVEL_MASK    0x07


/*  #define     debug fatal  */

struct pcc2_data {
        struct interrupt        cpu_irq;

        uint8_t                 pcctwo_reg[PCC2_SIZE];

        uint8_t                 cur_int_vec;
};


static void reassert_interrupts(struct pcc2_data *d)
{
        /*  Block interrupts at the mask level or lower:  */
        if ((d->pcctwo_reg[PCCTWO_IPL] & INTERRUPT_LEVEL_MASK) <=
            (d->pcctwo_reg[PCCTWO_MASK] & INTERRUPT_LEVEL_MASK))
                INTERRUPT_DEASSERT(d->cpu_irq);
        else
                INTERRUPT_ASSERT(d->cpu_irq);
}


DEVICE_ACCESS(pcc2)
{
        uint64_t idata = 0, odata = 0;
        struct pcc2_data *d = extra;

        /*  0xfff42000..0xfff42fff, but only 0x40 unique registers:  */
        relative_addr %= PCC2_SIZE;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        if (writeflag == MEM_READ)
                odata = d->pcctwo_reg[relative_addr];

        switch (relative_addr) {

        case PCCTWO_CHIPID:
        case PCCTWO_CHIPREV:
                if (writeflag == MEM_WRITE) {
                        fatal("TODO: write to PCCTWO_CHIPID or CHIPREV?\n");
                        exit(1);
                }
                break;

        case PCCTWO_VECBASE:
                if (writeflag == MEM_WRITE) {
                        d->pcctwo_reg[PCCTWO_VECBASE] = idata & 0xf0;
                        if (idata & ~0xf0)
                                fatal("[ pcc2: HUH? write to PCCTWO_VECBASE"
                                    " with value 0x%02x. ]\n", (int) idata);
                }
                break;

        case PCCTWO_IPL:
                if (writeflag == MEM_WRITE) {
                        fatal("[ pcc2: HUH? Write attempt to PCCTWO_IPL. ]\n");
                }
                break;

        case PCCTWO_MASK:
                if (writeflag == MEM_WRITE) {
                        d->pcctwo_reg[relative_addr] = idata;
                        reassert_interrupts(d);
                }
                break;

        default:
                debug("[ pcc2: unimplemented %s offset 0x%x",
                    writeflag == MEM_WRITE? "write to" : "read from",
                    (int) relative_addr);
                if (writeflag == MEM_WRITE)
                        debug(": 0x%x", (int)idata);
                debug(" ]\n");
                /*  exit(1);  */
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


DEVICE_ACCESS(mvme187_iack)
{
        uint64_t odata = 0;
        struct pcc2_data *d = extra;

        if (writeflag == MEM_WRITE) {
                fatal("[ pcc2: write to mvme187_iack? ]\n");
        } else {
                odata = d->cur_int_vec;
                memory_writemax64(cpu, data, len, odata);
        }

        return 1;
}


DEVINIT(pcc2)
{
        struct pcc2_data *d;

        CHECK_ALLOCATION(d = malloc(sizeof(struct pcc2_data)));
        memset(d, 0, sizeof(struct pcc2_data));

        /*  Initial values, according to the manual:  */
        d->pcctwo_reg[PCCTWO_CHIPID] = PCC2_ID;
        d->pcctwo_reg[PCCTWO_CHIPREV] = 0x00;
        d->pcctwo_reg[PCCTWO_VECBASE] = 0x0f;

        /*  Connect to the CPU's interrupt pin:  */
        INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);

        memory_device_register(devinit->machine->memory, "pcc2",
            devinit->addr, 4096, dev_pcc2_access, (void *)d,
            DM_DEFAULT, NULL);

        memory_device_register(devinit->machine->memory, "mvme187_iack",
            M187_IACK, 32, dev_mvme187_iack_access, (void *)d,
            DM_DEFAULT, NULL);

        return 1;
}

1	/*
2	* Copyright (C) 2007 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: dev_pcc2.c,v 1.6 2007/08/29 20:36:49 debug Exp $
29	*
30	* COMMENT: Peripheral Channel Controller (PCC2) bus (used in MVME machines)
31	*
32	* See "Single Board Computers Programmer's Reference Guide (Part 2 of 2)",
33	* "VMESBCA2/PG1" (vmesbcp2.pdf) for more details.
34	*
35	* Note: This is somewhat MVME187-specific, at the moment.
36	*
37	*
38	* TODO: Lots of stuff.
39	*/
40
41	#include <stdio.h>
42	#include <stdlib.h>
43	#include <string.h>
44
45	#include "cpu.h"
46	#include "device.h"
47	#include "emul.h"
48	#include "interrupt.h"
49	#include "machine.h"
50	#include "memory.h"
51	#include "misc.h"
52
53
54	#include "mvme187.h"
55	#include "mvme_pcctworeg.h"
56
57	#define INTERRUPT_LEVEL_MASK 0x07
58
59
60	/* #define debug fatal */
61
62	struct pcc2_data {
63	struct interrupt cpu_irq;
64
65	uint8_t pcctwo_reg[PCC2_SIZE];
66
67	uint8_t cur_int_vec;
68	};
69
70
71	static void reassert_interrupts(struct pcc2_data *d)
72	{
73	/* Block interrupts at the mask level or lower: */
74	if ((d->pcctwo_reg[PCCTWO_IPL] & INTERRUPT_LEVEL_MASK) <=
75	(d->pcctwo_reg[PCCTWO_MASK] & INTERRUPT_LEVEL_MASK))
76	INTERRUPT_DEASSERT(d->cpu_irq);
77	else
78	INTERRUPT_ASSERT(d->cpu_irq);
79	}
80
81
82	DEVICE_ACCESS(pcc2)
83	{
84	uint64_t idata = 0, odata = 0;
85	struct pcc2_data *d = extra;
86
87	/* 0xfff42000..0xfff42fff, but only 0x40 unique registers: */
88	relative_addr %= PCC2_SIZE;
89
90	if (writeflag == MEM_WRITE)
91	idata = memory_readmax64(cpu, data, len);
92
93	if (writeflag == MEM_READ)
94	odata = d->pcctwo_reg[relative_addr];
95
96	switch (relative_addr) {
97
98	case PCCTWO_CHIPID:
99	case PCCTWO_CHIPREV:
100	if (writeflag == MEM_WRITE) {
101	fatal("TODO: write to PCCTWO_CHIPID or CHIPREV?\n");
102	exit(1);
103	}
104	break;
105
106	case PCCTWO_VECBASE:
107	if (writeflag == MEM_WRITE) {
108	d->pcctwo_reg[PCCTWO_VECBASE] = idata & 0xf0;
109	if (idata & ~0xf0)
110	fatal("[ pcc2: HUH? write to PCCTWO_VECBASE"
111	" with value 0x%02x. ]\n", (int) idata);
112	}
113	break;
114
115	case PCCTWO_IPL:
116	if (writeflag == MEM_WRITE) {
117	fatal("[ pcc2: HUH? Write attempt to PCCTWO_IPL. ]\n");
118	}
119	break;
120
121	case PCCTWO_MASK:
122	if (writeflag == MEM_WRITE) {
123	d->pcctwo_reg[relative_addr] = idata;
124	reassert_interrupts(d);
125	}
126	break;
127
128	default:
129	debug("[ pcc2: unimplemented %s offset 0x%x",
130	writeflag == MEM_WRITE? "write to" : "read from",
131	(int) relative_addr);
132	if (writeflag == MEM_WRITE)
133	debug(": 0x%x", (int)idata);
134	debug(" ]\n");
135	/* exit(1); */
136	}
137
138	if (writeflag == MEM_READ)
139	memory_writemax64(cpu, data, len, odata);
140
141	return 1;
142	}
143
144
145	DEVICE_ACCESS(mvme187_iack)
146	{
147	uint64_t odata = 0;
148	struct pcc2_data *d = extra;
149
150	if (writeflag == MEM_WRITE) {
151	fatal("[ pcc2: write to mvme187_iack? ]\n");
152	} else {
153	odata = d->cur_int_vec;
154	memory_writemax64(cpu, data, len, odata);
155	}
156
157	return 1;
158	}
159
160
161	DEVINIT(pcc2)
162	{
163	struct pcc2_data *d;
164
165	CHECK_ALLOCATION(d = malloc(sizeof(struct pcc2_data)));
166	memset(d, 0, sizeof(struct pcc2_data));
167
168	/* Initial values, according to the manual: */
169	d->pcctwo_reg[PCCTWO_CHIPID] = PCC2_ID;
170	d->pcctwo_reg[PCCTWO_CHIPREV] = 0x00;
171	d->pcctwo_reg[PCCTWO_VECBASE] = 0x0f;
172
173	/* Connect to the CPU's interrupt pin: */
174	INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
175
176	memory_device_register(devinit->machine->memory, "pcc2",
177	devinit->addr, 4096, dev_pcc2_access, (void *)d,
178	DM_DEFAULT, NULL);
179
180	memory_device_register(devinit->machine->memory, "mvme187_iack",
181	M187_IACK, 32, dev_mvme187_iack_access, (void *)d,
182	DM_DEFAULT, NULL);
183
184	return 1;
185	}
186