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dpavlin |
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/* |
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* Copyright (C) 2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: dev_pcc2.c,v 1.6 2007/08/29 20:36:49 debug Exp $ |
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dpavlin |
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* |
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dpavlin |
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* COMMENT: Peripheral Channel Controller (PCC2) bus (used in MVME machines) |
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dpavlin |
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* |
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dpavlin |
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* See "Single Board Computers Programmer's Reference Guide (Part 2 of 2)", |
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* "VMESBCA2/PG1" (vmesbcp2.pdf) for more details. |
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* |
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* Note: This is somewhat MVME187-specific, at the moment. |
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* |
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* |
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* TODO: Lots of stuff. |
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dpavlin |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "cpu.h" |
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#include "device.h" |
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#include "emul.h" |
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dpavlin |
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#include "interrupt.h" |
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dpavlin |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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dpavlin |
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#include "mvme187.h" |
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dpavlin |
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#include "mvme_pcctworeg.h" |
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dpavlin |
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#define INTERRUPT_LEVEL_MASK 0x07 |
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dpavlin |
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dpavlin |
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dpavlin |
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/* #define debug fatal */ |
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struct pcc2_data { |
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dpavlin |
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struct interrupt cpu_irq; |
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dpavlin |
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uint8_t pcctwo_reg[PCC2_SIZE]; |
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dpavlin |
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uint8_t cur_int_vec; |
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}; |
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dpavlin |
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static void reassert_interrupts(struct pcc2_data *d) |
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{ |
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/* Block interrupts at the mask level or lower: */ |
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if ((d->pcctwo_reg[PCCTWO_IPL] & INTERRUPT_LEVEL_MASK) <= |
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(d->pcctwo_reg[PCCTWO_MASK] & INTERRUPT_LEVEL_MASK)) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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else |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
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dpavlin |
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DEVICE_ACCESS(pcc2) |
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{ |
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uint64_t idata = 0, odata = 0; |
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struct pcc2_data *d = extra; |
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dpavlin |
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/* 0xfff42000..0xfff42fff, but only 0x40 unique registers: */ |
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relative_addr %= PCC2_SIZE; |
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dpavlin |
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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if (writeflag == MEM_READ) |
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odata = d->pcctwo_reg[relative_addr]; |
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switch (relative_addr) { |
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case PCCTWO_CHIPID: |
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case PCCTWO_CHIPREV: |
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if (writeflag == MEM_WRITE) { |
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fatal("TODO: write to PCCTWO_CHIPID or CHIPREV?\n"); |
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exit(1); |
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} |
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break; |
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case PCCTWO_VECBASE: |
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dpavlin |
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if (writeflag == MEM_WRITE) { |
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d->pcctwo_reg[PCCTWO_VECBASE] = idata & 0xf0; |
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if (idata & ~0xf0) |
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fatal("[ pcc2: HUH? write to PCCTWO_VECBASE" |
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" with value 0x%02x. ]\n", (int) idata); |
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} |
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dpavlin |
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break; |
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dpavlin |
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case PCCTWO_IPL: |
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if (writeflag == MEM_WRITE) { |
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fatal("[ pcc2: HUH? Write attempt to PCCTWO_IPL. ]\n"); |
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} |
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break; |
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dpavlin |
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case PCCTWO_MASK: |
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if (writeflag == MEM_WRITE) { |
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d->pcctwo_reg[relative_addr] = idata; |
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dpavlin |
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reassert_interrupts(d); |
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dpavlin |
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} |
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break; |
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dpavlin |
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default: |
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debug("[ pcc2: unimplemented %s offset 0x%x", |
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writeflag == MEM_WRITE? "write to" : "read from", |
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(int) relative_addr); |
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if (writeflag == MEM_WRITE) |
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debug(": 0x%x", (int)idata); |
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debug(" ]\n"); |
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/* exit(1); */ |
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} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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dpavlin |
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DEVICE_ACCESS(mvme187_iack) |
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{ |
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uint64_t odata = 0; |
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struct pcc2_data *d = extra; |
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if (writeflag == MEM_WRITE) { |
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fatal("[ pcc2: write to mvme187_iack? ]\n"); |
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} else { |
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odata = d->cur_int_vec; |
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memory_writemax64(cpu, data, len, odata); |
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} |
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return 1; |
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} |
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dpavlin |
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DEVINIT(pcc2) |
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{ |
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struct pcc2_data *d; |
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CHECK_ALLOCATION(d = malloc(sizeof(struct pcc2_data))); |
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memset(d, 0, sizeof(struct pcc2_data)); |
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dpavlin |
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/* Initial values, according to the manual: */ |
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dpavlin |
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d->pcctwo_reg[PCCTWO_CHIPID] = PCC2_ID; |
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dpavlin |
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d->pcctwo_reg[PCCTWO_CHIPREV] = 0x00; |
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d->pcctwo_reg[PCCTWO_VECBASE] = 0x0f; |
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dpavlin |
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dpavlin |
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/* Connect to the CPU's interrupt pin: */ |
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INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq); |
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dpavlin |
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memory_device_register(devinit->machine->memory, "pcc2", |
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dpavlin |
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devinit->addr, 4096, dev_pcc2_access, (void *)d, |
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DM_DEFAULT, NULL); |
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dpavlin |
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memory_device_register(devinit->machine->memory, "mvme187_iack", |
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M187_IACK, 32, dev_mvme187_iack_access, (void *)d, |
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DM_DEFAULT, NULL); |
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dpavlin |
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return 1; |
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} |
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