/[gxemul]/trunk/src/devices/dev_openpic.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/devices/dev_openpic.c

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Revision 73 - (show annotations)
Sun Oct 14 18:35:57 2007 UTC (11 years, 7 months ago) by dpavlin
File MIME type: text/plain
File size: 9466 byte(s)
try to decode vector from offset... doesn't work for external irqs
1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $
28 *
29 * COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc)
30 * based on dev_gc.c
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36
37 #include "cpu.h"
38 #include "device.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42
43
44 #define DEV_OPENPIC_LENGTH 0x40000
45
46 struct openpic_data {
47 struct interrupt cpu_irq;
48
49 uint32_t status_hi;
50 uint32_t status_lo;
51 uint32_t enable_hi;
52 uint32_t enable_lo;
53 };
54
55
56 void openpic_hi_interrupt_assert(struct interrupt *interrupt)
57 {
58 struct openpic_data *d = interrupt->extra;
59 d->status_hi |= interrupt->line;
60 if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
61 INTERRUPT_ASSERT(d->cpu_irq);
62 }
63 void openpic_hi_interrupt_deassert(struct interrupt *interrupt)
64 {
65 struct openpic_data *d = interrupt->extra;
66 d->status_hi &= ~interrupt->line;
67 if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
68 INTERRUPT_DEASSERT(d->cpu_irq);
69 }
70 void openpic_lo_interrupt_assert(struct interrupt *interrupt)
71 {
72 struct openpic_data *d = interrupt->extra;
73 d->status_lo |= interrupt->line;
74 if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
75 INTERRUPT_ASSERT(d->cpu_irq);
76 }
77 void openpic_lo_interrupt_deassert(struct interrupt *interrupt)
78 {
79 struct openpic_data *d = interrupt->extra;
80 d->status_lo &= ~interrupt->line;
81 if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
82 INTERRUPT_DEASSERT(d->cpu_irq);
83 }
84
85 /*
86 * FIXME acitvity is never sat
87 */
88
89 #define OPENPIC_MASK 0x80000000
90 #define OPENPIC_ACTIVITY 0x40000000 /* Read Only */
91 #define OPENPIC_PRIORITY_MASK 0x000f0000
92 #define OPENPIC_PRIORITY_SHIFT 16
93 #define OPENPIC_VECTOR_MASK 0x000000ff
94
95 #define OPENPIC_VEC_TIMER 64 /* and up */
96 #define OPENPIC_VEC_IPI 72 /* and up */
97 #define OPENPIC_VEC_SPURIOUS 127
98
99 #define OPENPIC_NUM_TIMERS 4
100 #define OPENPIC_NUM_IPI 4
101 #define OPENPIC_NUM_PRI 16
102 #define OPENPIC_NUM_VECTORS 256
103
104 DEVICE_ACCESS(openpic)
105 {
106 // struct openpic_data *d = extra;
107 uint64_t idata = 0, odata = 0;
108
109 if (writeflag == MEM_WRITE) {
110 idata = memory_readmax64(cpu, data, len);
111 // shuffle byte order
112 idata =
113 ( idata & 0x000000ff ) << 24 |
114 ( idata & 0x0000ff00 ) << 8 |
115 ( idata & 0x00ff0000 ) >> 8 |
116 ( idata & 0xff000000 ) >> 24 ;
117
118 uint64_t priority,vector, active;
119 priority = ( idata & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT;
120 vector = ( idata & OPENPIC_VECTOR_MASK );
121 active = ( idata & OPENPIC_ACTIVITY );
122
123 debug("[ openpic: WRITE %05x | %08x | priority: %x vector: 0x%02x %d active: %x ]\n",
124 (int)relative_addr, (int)idata, (int)priority, (int)vector, (int)vector, (int)active );
125 }
126
127 switch (relative_addr) {
128
129 // version
130 case 0x00:
131 if (writeflag == MEM_READ) {
132 // version 1.x, so 2 -> 1.2
133 odata = 2;
134 debug("[ openpic: read version "
135 "offset 0x%x = 1.%d]\n", (int)
136 relative_addr, (int)odata);
137 odata |= 0x00190000; // FIXME ?
138
139 }
140 fatal("[ openpic: unimplemented write to "
141 "offset 0x%x: data=0x%x (OpenPIC version) ]\n", (int)
142 relative_addr, (int)idata);
143 break;
144
145 // global timer frequency
146 case 0xf0:
147 if (writeflag == MEM_READ) {
148 // this would be correct, but real DSM-G600 isn't
149 // returning it!
150 //odata = 170 * 1000000; // MHz
151 odata = 0;
152 debug("[ openpic: read global timer frequency "
153 "offset 0x%x = %x]\n", (int)
154 relative_addr, (int)odata);
155 }
156 fatal("[ openpic: unimplemented write to "
157 "offset 0x%x: data=0x%x ]\n", (int)
158 relative_addr, (int)idata);
159 break;
160
161 #if 0
162 #define INT_STATE_REG_H (interrupt_reg + 0x00)
163 #define INT_ENABLE_REG_H (interrupt_reg + 0x04)
164 #define INT_CLEAR_REG_H (interrupt_reg + 0x08)
165 #define INT_LEVEL_REG_H (interrupt_reg + 0x0c)
166 #define INT_STATE_REG_L (interrupt_reg + 0x10)
167 #define INT_ENABLE_REG_L (interrupt_reg + 0x14)
168 #define INT_CLEAR_REG_L (interrupt_reg + 0x18)
169 #define INT_LEVEL_REG_L (interrupt_reg + 0x1c)
170
171 case 0x10:
172 if (writeflag == MEM_READ)
173 odata = d->status_hi & d->enable_hi;
174 break;
175
176 case 0x14:
177 if (writeflag == MEM_READ)
178 odata = d->enable_hi;
179 else {
180 int old_assert = (d->status_lo & d->enable_lo
181 || d->status_hi & d->enable_hi);
182 int new_assert;
183 d->enable_hi = idata;
184
185 new_assert = (d->status_lo & d->enable_lo ||
186 d->status_hi & d->enable_hi);
187
188 if (old_assert && !new_assert)
189 INTERRUPT_DEASSERT(d->cpu_irq);
190 else if (!old_assert && new_assert)
191 INTERRUPT_ASSERT(d->cpu_irq);
192 }
193 break;
194
195 case 0x18:
196 if (writeflag == MEM_WRITE) {
197 int old_assert = (d->status_lo & d->enable_lo
198 || d->status_hi & d->enable_hi);
199 int new_assert;
200 d->status_hi &= ~idata;
201
202 new_assert = (d->status_lo & d->enable_lo ||
203 d->status_hi & d->enable_hi);
204
205 if (old_assert && !new_assert)
206 INTERRUPT_DEASSERT(d->cpu_irq);
207 else if (!old_assert && new_assert)
208 INTERRUPT_ASSERT(d->cpu_irq);
209 }
210 break;
211
212 case 0x20:
213 if (writeflag == MEM_READ)
214 odata = d->status_lo & d->enable_lo;
215 break;
216
217 case 0x24:
218 if (writeflag == MEM_READ)
219 odata = d->enable_lo;
220 else {
221 int old_assert = (d->status_lo & d->enable_lo
222 || d->status_hi & d->enable_hi);
223 int new_assert;
224 d->enable_lo = idata;
225
226 new_assert = (d->status_lo & d->enable_lo ||
227 d->status_hi & d->enable_hi);
228
229 if (old_assert && !new_assert)
230 INTERRUPT_DEASSERT(d->cpu_irq);
231 else if (!old_assert && new_assert)
232 INTERRUPT_ASSERT(d->cpu_irq);
233 }
234 break;
235
236 case 0x28:
237 if (writeflag == MEM_WRITE) {
238 int old_assert = (d->status_lo & d->enable_lo
239 || d->status_hi & d->enable_hi);
240 int new_assert;
241 d->status_lo &= ~idata;
242
243 new_assert = (d->status_lo & d->enable_lo ||
244 d->status_hi & d->enable_hi);
245
246 if (old_assert && !new_assert)
247 INTERRUPT_DEASSERT(d->cpu_irq);
248 else if (!old_assert && new_assert)
249 INTERRUPT_ASSERT(d->cpu_irq);
250 }
251 break;
252
253 case 0x1c:
254 case 0x2c:
255 /* Avoid a debug message. */
256 break;
257 #endif
258 default:
259 if (writeflag == MEM_WRITE) {
260 fatal("[ openpic: unimplemented write to "
261 "offset 0x%x idata = %x ]\n",
262 (int)relative_addr, (int)idata
263 );
264 } else {
265 // decoded from real device
266 odata |= OPENPIC_MASK;
267
268 int vec =
269 (
270 (
271 (
272 (
273 ( relative_addr - 0x120 ) & 0xfff
274 ) / 0x40
275 )
276 ) & 0xff
277 ) + 0x40;
278
279 odata |= vec;
280
281 debug("[ openpic: unimplemented read from "
282 "offset 0x%x decoded vec = 0x%02x %d odata = %x ]\n",
283 (int)relative_addr, vec, vec, (int)odata
284 );
285 }
286 }
287
288 if (writeflag == MEM_READ) {
289
290 debug("[ openpic: READ %05x | %08x ]\n",
291 (int)relative_addr, (int)odata
292 );
293
294 // shuffle byte order
295 odata =
296 ( odata & 0x000000ff ) << 24 |
297 ( odata & 0x0000ff00 ) << 8 |
298 ( odata & 0x00ff0000 ) >> 8 |
299 ( odata & 0xff000000 ) >> 24 ;
300 memory_writemax64(cpu, data, len, odata);
301 }
302
303 return 1;
304 }
305
306
307 DEVINIT(openpic)
308 {
309 struct openpic_data *d;
310 int i;
311
312 CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data)));
313 memset(d, 0, sizeof(struct openpic_data));
314
315 /* Connect to the CPU interrupt pin: */
316 INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
317
318 /*
319 * Register the 126 OpenPIC interrupts
320 */
321 for (i=0; i<126; i++) {
322 struct interrupt template;
323 char n[300];
324 snprintf(n, sizeof(n), "%s.openpic.%i",
325 devinit->interrupt_path, i);
326 memset(&template, 0, sizeof(template));
327 template.line = 1 << i;
328 template.name = n;
329 template.extra = d;
330 template.interrupt_assert = openpic_lo_interrupt_assert;
331 template.interrupt_deassert = openpic_lo_interrupt_deassert;
332 interrupt_handler_register(&template);
333 // debug("[ openpic: added interrupt %s ]\n", n);
334 }
335
336 memory_device_register(devinit->machine->memory, "openpic",
337 devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL);
338
339 return 1;
340 }
341

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