/[gxemul]/trunk/src/devices/dev_openpic.c
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Contents of /trunk/src/devices/dev_openpic.c

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Revision 71 - (show annotations)
Sun Oct 14 16:53:47 2007 UTC (11 years, 8 months ago) by dpavlin
File MIME type: text/plain
File size: 9103 byte(s)
so don't split debug here
1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $
28 *
29 * COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc)
30 * based on dev_gc.c
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36
37 #include "cpu.h"
38 #include "device.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42
43
44 #define DEV_OPENPIC_LENGTH 0x40000
45
46 struct openpic_data {
47 struct interrupt cpu_irq;
48
49 uint32_t status_hi;
50 uint32_t status_lo;
51 uint32_t enable_hi;
52 uint32_t enable_lo;
53 };
54
55
56 void openpic_hi_interrupt_assert(struct interrupt *interrupt)
57 {
58 struct openpic_data *d = interrupt->extra;
59 d->status_hi |= interrupt->line;
60 if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
61 INTERRUPT_ASSERT(d->cpu_irq);
62 }
63 void openpic_hi_interrupt_deassert(struct interrupt *interrupt)
64 {
65 struct openpic_data *d = interrupt->extra;
66 d->status_hi &= ~interrupt->line;
67 if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
68 INTERRUPT_DEASSERT(d->cpu_irq);
69 }
70 void openpic_lo_interrupt_assert(struct interrupt *interrupt)
71 {
72 struct openpic_data *d = interrupt->extra;
73 d->status_lo |= interrupt->line;
74 if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
75 INTERRUPT_ASSERT(d->cpu_irq);
76 }
77 void openpic_lo_interrupt_deassert(struct interrupt *interrupt)
78 {
79 struct openpic_data *d = interrupt->extra;
80 d->status_lo &= ~interrupt->line;
81 if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
82 INTERRUPT_DEASSERT(d->cpu_irq);
83 }
84
85 /*
86 * FIXME acitvity is never sat
87 */
88
89 #define OPENPIC_MASK 0x80000000
90 #define OPENPIC_ACTIVITY 0x40000000 /* Read Only */
91 #define OPENPIC_PRIORITY_MASK 0x000f0000
92 #define OPENPIC_PRIORITY_SHIFT 16
93 #define OPENPIC_VECTOR_MASK 0x000000ff
94
95 #define OPENPIC_VEC_TIMER 64 /* and up */
96 #define OPENPIC_VEC_IPI 72 /* and up */
97 #define OPENPIC_VEC_SPURIOUS 127
98
99 #define OPENPIC_NUM_TIMERS 4
100 #define OPENPIC_NUM_IPI 4
101 #define OPENPIC_NUM_PRI 16
102 #define OPENPIC_NUM_VECTORS 256
103
104 DEVICE_ACCESS(openpic)
105 {
106 // struct openpic_data *d = extra;
107 uint64_t idata = 0, odata = 0;
108
109 if (writeflag == MEM_WRITE) {
110 idata = memory_readmax64(cpu, data, len);
111 // shuffle byte order
112 idata =
113 ( idata & 0x000000ff ) << 24 |
114 ( idata & 0x0000ff00 ) << 8 |
115 ( idata & 0x00ff0000 ) >> 8 |
116 ( idata & 0xff000000 ) >> 24 ;
117
118 uint64_t priority,vector, active;
119 priority = ( idata & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT;
120 vector = ( idata & OPENPIC_VECTOR_MASK );
121 active = ( idata & OPENPIC_ACTIVITY );
122
123 debug("[ openpic: WRITE %05x | %08x | priority: %x vector: 0x%02x %d active: %x ]\n",
124 (int)relative_addr, (int)idata, (int)priority, (int)vector, (int)vector, (int)active );
125 }
126
127 switch (relative_addr) {
128
129 // version
130 case 0x00:
131 if (writeflag == MEM_READ) {
132 // version 1.x, so 2 -> 1.2
133 odata = 2;
134 fatal("[ openpic: read version "
135 "offset 0x%x = 1.%d]\n", (int)
136 relative_addr, (int)odata);
137 }
138 fatal("[ openpic: unimplemented write to "
139 "offset 0x%x: data=0x%x (OpenPIC version) ]\n", (int)
140 relative_addr, (int)idata);
141 break;
142
143 // global timer frequency
144 case 0xf0:
145 if (writeflag == MEM_READ) {
146 odata = 170 * 1000000; // MHz
147 fatal("[ openpic: read global timer frequency "
148 "offset 0x%x = %x]\n", (int)
149 relative_addr, (int)odata);
150 }
151 fatal("[ openpic: unimplemented write to "
152 "offset 0x%x: data=0x%x ]\n", (int)
153 relative_addr, (int)idata);
154 break;
155
156 #if 0
157 #define INT_STATE_REG_H (interrupt_reg + 0x00)
158 #define INT_ENABLE_REG_H (interrupt_reg + 0x04)
159 #define INT_CLEAR_REG_H (interrupt_reg + 0x08)
160 #define INT_LEVEL_REG_H (interrupt_reg + 0x0c)
161 #define INT_STATE_REG_L (interrupt_reg + 0x10)
162 #define INT_ENABLE_REG_L (interrupt_reg + 0x14)
163 #define INT_CLEAR_REG_L (interrupt_reg + 0x18)
164 #define INT_LEVEL_REG_L (interrupt_reg + 0x1c)
165
166 case 0x10:
167 if (writeflag == MEM_READ)
168 odata = d->status_hi & d->enable_hi;
169 break;
170
171 case 0x14:
172 if (writeflag == MEM_READ)
173 odata = d->enable_hi;
174 else {
175 int old_assert = (d->status_lo & d->enable_lo
176 || d->status_hi & d->enable_hi);
177 int new_assert;
178 d->enable_hi = idata;
179
180 new_assert = (d->status_lo & d->enable_lo ||
181 d->status_hi & d->enable_hi);
182
183 if (old_assert && !new_assert)
184 INTERRUPT_DEASSERT(d->cpu_irq);
185 else if (!old_assert && new_assert)
186 INTERRUPT_ASSERT(d->cpu_irq);
187 }
188 break;
189
190 case 0x18:
191 if (writeflag == MEM_WRITE) {
192 int old_assert = (d->status_lo & d->enable_lo
193 || d->status_hi & d->enable_hi);
194 int new_assert;
195 d->status_hi &= ~idata;
196
197 new_assert = (d->status_lo & d->enable_lo ||
198 d->status_hi & d->enable_hi);
199
200 if (old_assert && !new_assert)
201 INTERRUPT_DEASSERT(d->cpu_irq);
202 else if (!old_assert && new_assert)
203 INTERRUPT_ASSERT(d->cpu_irq);
204 }
205 break;
206
207 case 0x20:
208 if (writeflag == MEM_READ)
209 odata = d->status_lo & d->enable_lo;
210 break;
211
212 case 0x24:
213 if (writeflag == MEM_READ)
214 odata = d->enable_lo;
215 else {
216 int old_assert = (d->status_lo & d->enable_lo
217 || d->status_hi & d->enable_hi);
218 int new_assert;
219 d->enable_lo = idata;
220
221 new_assert = (d->status_lo & d->enable_lo ||
222 d->status_hi & d->enable_hi);
223
224 if (old_assert && !new_assert)
225 INTERRUPT_DEASSERT(d->cpu_irq);
226 else if (!old_assert && new_assert)
227 INTERRUPT_ASSERT(d->cpu_irq);
228 }
229 break;
230
231 case 0x28:
232 if (writeflag == MEM_WRITE) {
233 int old_assert = (d->status_lo & d->enable_lo
234 || d->status_hi & d->enable_hi);
235 int new_assert;
236 d->status_lo &= ~idata;
237
238 new_assert = (d->status_lo & d->enable_lo ||
239 d->status_hi & d->enable_hi);
240
241 if (old_assert && !new_assert)
242 INTERRUPT_DEASSERT(d->cpu_irq);
243 else if (!old_assert && new_assert)
244 INTERRUPT_ASSERT(d->cpu_irq);
245 }
246 break;
247
248 case 0x1c:
249 case 0x2c:
250 /* Avoid a debug message. */
251 break;
252 #endif
253 default:
254 if (writeflag == MEM_WRITE) {
255 fatal("[ openpic: unimplemented write to "
256 "offset 0x%x idata = %x ]\n",
257 (int)relative_addr, (int)idata
258 );
259 } else {
260 fatal("[ openpic: unimplemented read from "
261 "offset 0x%x odata = %x ]\n",
262 (int)relative_addr, (int)odata
263 );
264 }
265 }
266
267 if (writeflag == MEM_READ) {
268 // shuffle byte order
269 odata =
270 ( odata & 0x000000ff ) << 24 |
271 ( odata & 0x0000ff00 ) << 8 |
272 ( odata & 0x00ff0000 ) >> 8 |
273 ( odata & 0xff000000 ) >> 24 ;
274 memory_writemax64(cpu, data, len, odata);
275 debug("[ openpic: READ %05x | %08x ]\n",
276 (int)relative_addr, (int)odata
277 );
278 }
279
280 return 1;
281 }
282
283
284 DEVINIT(openpic)
285 {
286 struct openpic_data *d;
287 int i;
288
289 CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data)));
290 memset(d, 0, sizeof(struct openpic_data));
291
292 /* Connect to the CPU interrupt pin: */
293 INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
294
295 /*
296 * Register the 126 OpenPIC interrupts
297 */
298 for (i=0; i<126; i++) {
299 struct interrupt template;
300 char n[300];
301 snprintf(n, sizeof(n), "%s.openpic.%i",
302 devinit->interrupt_path, i);
303 memset(&template, 0, sizeof(template));
304 template.line = 1 << i;
305 template.name = n;
306 template.extra = d;
307 template.interrupt_assert = openpic_lo_interrupt_assert;
308 template.interrupt_deassert = openpic_lo_interrupt_deassert;
309 interrupt_handler_register(&template);
310 // debug("[ openpic: added interrupt %s ]\n", n);
311 }
312
313 memory_device_register(devinit->machine->memory, "openpic",
314 devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL);
315
316 return 1;
317 }
318

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