/[gxemul]/trunk/src/devices/dev_openpic.c
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Contents of /trunk/src/devices/dev_openpic.c

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Revision 66 - (show annotations)
Sun Oct 14 12:03:25 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 8003 byte(s)
more openpic tweaking and collecting usefull references
1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $
28 *
29 * COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc)
30 * based on dev_gc.c
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36
37 #include "cpu.h"
38 #include "device.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42
43
44 #define DEV_OPENPIC_LENGTH 0x40000
45
46 struct openpic_data {
47 struct interrupt cpu_irq;
48
49 uint32_t status_hi;
50 uint32_t status_lo;
51 uint32_t enable_hi;
52 uint32_t enable_lo;
53 };
54
55
56 void openpic_hi_interrupt_assert(struct interrupt *interrupt)
57 {
58 struct openpic_data *d = interrupt->extra;
59 d->status_hi |= interrupt->line;
60 if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
61 INTERRUPT_ASSERT(d->cpu_irq);
62 }
63 void openpic_hi_interrupt_deassert(struct interrupt *interrupt)
64 {
65 struct openpic_data *d = interrupt->extra;
66 d->status_hi &= ~interrupt->line;
67 if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
68 INTERRUPT_DEASSERT(d->cpu_irq);
69 }
70 void openpic_lo_interrupt_assert(struct interrupt *interrupt)
71 {
72 struct openpic_data *d = interrupt->extra;
73 d->status_lo |= interrupt->line;
74 if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
75 INTERRUPT_ASSERT(d->cpu_irq);
76 }
77 void openpic_lo_interrupt_deassert(struct interrupt *interrupt)
78 {
79 struct openpic_data *d = interrupt->extra;
80 d->status_lo &= ~interrupt->line;
81 if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
82 INTERRUPT_DEASSERT(d->cpu_irq);
83 }
84
85 #define OPENPIC_MASK 0x80000000
86 #define OPENPIC_ACTIVITY 0x40000000 /* Read Only */
87 #define OPENPIC_PRIORITY_MASK 0x000f0000
88 #define OPENPIC_PRIORITY_SHIFT 16
89 #define OPENPIC_VECTOR_MASK 0x000000ff
90
91 #define OPENPIC_VEC_TIMER 64 /* and up */
92 #define OPENPIC_VEC_IPI 72 /* and up */
93 #define OPENPIC_VEC_SPURIOUS 127
94
95 DEVICE_ACCESS(openpic)
96 {
97 // struct openpic_data *d = extra;
98 uint64_t idata = 0, odata = 0;
99
100 if (writeflag == MEM_WRITE)
101 idata = memory_readmax64(cpu, data, len);
102
103 uint64_t priority,vector, active;
104 priority = ( relative_addr & 0xf000 );
105 vector = ( relative_addr & 0x00ff );
106 active = ( relative_addr & 0x4000 );
107
108 debug("[ openpic: access at %04x -> priority: %x vector: 0x%02x %d active: %x ]\n",
109 (int)relative_addr, (int)priority, (int)vector, (int)vector, (int)active );
110
111 switch (relative_addr) {
112
113 case 0x00:
114 if (writeflag == MEM_READ) {
115 // version 1.2
116 odata = 0x02000000;
117 fatal("[ openpic: read from "
118 "offset 0x%x (OpenPIC version) = %x]\n", (int)
119 relative_addr, (int)odata);
120 }
121 fatal("[ openpic: unimplemented write to "
122 "offset 0x%x: data=0x%x (OpenPIC version) ]\n", (int)
123 relative_addr, (int)idata);
124 break;
125
126 #if 0
127 #define INT_STATE_REG_H (interrupt_reg + 0x00)
128 #define INT_ENABLE_REG_H (interrupt_reg + 0x04)
129 #define INT_CLEAR_REG_H (interrupt_reg + 0x08)
130 #define INT_LEVEL_REG_H (interrupt_reg + 0x0c)
131 #define INT_STATE_REG_L (interrupt_reg + 0x10)
132 #define INT_ENABLE_REG_L (interrupt_reg + 0x14)
133 #define INT_CLEAR_REG_L (interrupt_reg + 0x18)
134 #define INT_LEVEL_REG_L (interrupt_reg + 0x1c)
135 #endif
136
137 #if 0
138 case 0x10:
139 if (writeflag == MEM_READ)
140 odata = d->status_hi & d->enable_hi;
141 break;
142
143 case 0x14:
144 if (writeflag == MEM_READ)
145 odata = d->enable_hi;
146 else {
147 int old_assert = (d->status_lo & d->enable_lo
148 || d->status_hi & d->enable_hi);
149 int new_assert;
150 d->enable_hi = idata;
151
152 new_assert = (d->status_lo & d->enable_lo ||
153 d->status_hi & d->enable_hi);
154
155 if (old_assert && !new_assert)
156 INTERRUPT_DEASSERT(d->cpu_irq);
157 else if (!old_assert && new_assert)
158 INTERRUPT_ASSERT(d->cpu_irq);
159 }
160 break;
161
162 case 0x18:
163 if (writeflag == MEM_WRITE) {
164 int old_assert = (d->status_lo & d->enable_lo
165 || d->status_hi & d->enable_hi);
166 int new_assert;
167 d->status_hi &= ~idata;
168
169 new_assert = (d->status_lo & d->enable_lo ||
170 d->status_hi & d->enable_hi);
171
172 if (old_assert && !new_assert)
173 INTERRUPT_DEASSERT(d->cpu_irq);
174 else if (!old_assert && new_assert)
175 INTERRUPT_ASSERT(d->cpu_irq);
176 }
177 break;
178
179 case 0x20:
180 if (writeflag == MEM_READ)
181 odata = d->status_lo & d->enable_lo;
182 break;
183
184 case 0x24:
185 if (writeflag == MEM_READ)
186 odata = d->enable_lo;
187 else {
188 int old_assert = (d->status_lo & d->enable_lo
189 || d->status_hi & d->enable_hi);
190 int new_assert;
191 d->enable_lo = idata;
192
193 new_assert = (d->status_lo & d->enable_lo ||
194 d->status_hi & d->enable_hi);
195
196 if (old_assert && !new_assert)
197 INTERRUPT_DEASSERT(d->cpu_irq);
198 else if (!old_assert && new_assert)
199 INTERRUPT_ASSERT(d->cpu_irq);
200 }
201 break;
202
203 case 0x28:
204 if (writeflag == MEM_WRITE) {
205 int old_assert = (d->status_lo & d->enable_lo
206 || d->status_hi & d->enable_hi);
207 int new_assert;
208 d->status_lo &= ~idata;
209
210 new_assert = (d->status_lo & d->enable_lo ||
211 d->status_hi & d->enable_hi);
212
213 if (old_assert && !new_assert)
214 INTERRUPT_DEASSERT(d->cpu_irq);
215 else if (!old_assert && new_assert)
216 INTERRUPT_ASSERT(d->cpu_irq);
217 }
218 break;
219
220 case 0x1c:
221 case 0x2c:
222 /* Avoid a debug message. */
223 break;
224 #endif
225 default:if (writeflag == MEM_WRITE) {
226 fatal("[ openpic: unimplemented write to "
227 "offset 0x%x: data=0x%x ]\n", (int)
228 relative_addr, (int)idata);
229 } else {
230 fatal("[ openpic: unimplemented read from "
231 "offset 0x%x ]\n", (int)relative_addr);
232 }
233 }
234
235 if (writeflag == MEM_READ)
236 memory_writemax64(cpu, data, len, odata);
237
238 return 1;
239 }
240
241
242 DEVINIT(openpic)
243 {
244 struct openpic_data *d;
245 int i;
246
247 CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data)));
248 memset(d, 0, sizeof(struct openpic_data));
249
250 /* Connect to the CPU interrupt pin: */
251 INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
252
253 /*
254 * Register the 126 OpenPIC interrupts
255 */
256 for (i=0; i<126; i++) {
257 struct interrupt template;
258 char n[300];
259 snprintf(n, sizeof(n), "%s.openpic.%i",
260 devinit->interrupt_path, i);
261 memset(&template, 0, sizeof(template));
262 template.line = 1 << i;
263 template.name = n;
264 template.extra = d;
265 template.interrupt_assert = openpic_lo_interrupt_assert;
266 template.interrupt_deassert = openpic_lo_interrupt_deassert;
267 interrupt_handler_register(&template);
268 }
269
270 memory_device_register(devinit->machine->memory, "openpic",
271 devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL);
272
273 return 1;
274 }
275

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