| 1 |
/* |
| 2 |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
| 3 |
* |
| 4 |
* Redistribution and use in source and binary forms, with or without |
| 5 |
* modification, are permitted provided that the following conditions are met: |
| 6 |
* |
| 7 |
* 1. Redistributions of source code must retain the above copyright |
| 8 |
* notice, this list of conditions and the following disclaimer. |
| 9 |
* 2. Redistributions in binary form must reproduce the above copyright |
| 10 |
* notice, this list of conditions and the following disclaimer in the |
| 11 |
* documentation and/or other materials provided with the distribution. |
| 12 |
* 3. The name of the author may not be used to endorse or promote products |
| 13 |
* derived from this software without specific prior written permission. |
| 14 |
* |
| 15 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 16 |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 18 |
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 19 |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 20 |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 21 |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 22 |
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 23 |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 24 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 25 |
* SUCH DAMAGE. |
| 26 |
* |
| 27 |
* $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $ |
| 28 |
* |
| 29 |
* COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc) |
| 30 |
* based on dev_gc.c |
| 31 |
*/ |
| 32 |
|
| 33 |
#include <stdio.h> |
| 34 |
#include <stdlib.h> |
| 35 |
#include <string.h> |
| 36 |
|
| 37 |
#include "cpu.h" |
| 38 |
#include "device.h" |
| 39 |
#include "machine.h" |
| 40 |
#include "memory.h" |
| 41 |
#include "misc.h" |
| 42 |
|
| 43 |
|
| 44 |
#define DEV_OPENPIC_LENGTH 0x40000 |
| 45 |
|
| 46 |
struct openpic_data { |
| 47 |
struct interrupt cpu_irq; |
| 48 |
|
| 49 |
uint32_t status_hi; |
| 50 |
uint32_t status_lo; |
| 51 |
uint32_t enable_hi; |
| 52 |
uint32_t enable_lo; |
| 53 |
}; |
| 54 |
|
| 55 |
|
| 56 |
void openpic_hi_interrupt_assert(struct interrupt *interrupt) |
| 57 |
{ |
| 58 |
struct openpic_data *d = interrupt->extra; |
| 59 |
d->status_hi |= interrupt->line; |
| 60 |
if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi) |
| 61 |
INTERRUPT_ASSERT(d->cpu_irq); |
| 62 |
} |
| 63 |
void openpic_hi_interrupt_deassert(struct interrupt *interrupt) |
| 64 |
{ |
| 65 |
struct openpic_data *d = interrupt->extra; |
| 66 |
d->status_hi &= ~interrupt->line; |
| 67 |
if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)) |
| 68 |
INTERRUPT_DEASSERT(d->cpu_irq); |
| 69 |
} |
| 70 |
void openpic_lo_interrupt_assert(struct interrupt *interrupt) |
| 71 |
{ |
| 72 |
struct openpic_data *d = interrupt->extra; |
| 73 |
d->status_lo |= interrupt->line; |
| 74 |
if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi) |
| 75 |
INTERRUPT_ASSERT(d->cpu_irq); |
| 76 |
} |
| 77 |
void openpic_lo_interrupt_deassert(struct interrupt *interrupt) |
| 78 |
{ |
| 79 |
struct openpic_data *d = interrupt->extra; |
| 80 |
d->status_lo &= ~interrupt->line; |
| 81 |
if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)) |
| 82 |
INTERRUPT_DEASSERT(d->cpu_irq); |
| 83 |
} |
| 84 |
|
| 85 |
|
| 86 |
DEVICE_ACCESS(openpic) |
| 87 |
{ |
| 88 |
// struct openpic_data *d = extra; |
| 89 |
uint64_t idata = 0, odata = 0; |
| 90 |
|
| 91 |
if (writeflag == MEM_WRITE) |
| 92 |
idata = memory_readmax64(cpu, data, len); |
| 93 |
|
| 94 |
switch (relative_addr) { |
| 95 |
|
| 96 |
case 0x00: |
| 97 |
if (writeflag == MEM_READ) |
| 98 |
// version 1.2 |
| 99 |
odata = 0x02000000; |
| 100 |
break; |
| 101 |
|
| 102 |
#if 0 |
| 103 |
#define INT_STATE_REG_H (interrupt_reg + 0x00) |
| 104 |
#define INT_ENABLE_REG_H (interrupt_reg + 0x04) |
| 105 |
#define INT_CLEAR_REG_H (interrupt_reg + 0x08) |
| 106 |
#define INT_LEVEL_REG_H (interrupt_reg + 0x0c) |
| 107 |
#define INT_STATE_REG_L (interrupt_reg + 0x10) |
| 108 |
#define INT_ENABLE_REG_L (interrupt_reg + 0x14) |
| 109 |
#define INT_CLEAR_REG_L (interrupt_reg + 0x18) |
| 110 |
#define INT_LEVEL_REG_L (interrupt_reg + 0x1c) |
| 111 |
#endif |
| 112 |
|
| 113 |
#if 0 |
| 114 |
case 0x10: |
| 115 |
if (writeflag == MEM_READ) |
| 116 |
odata = d->status_hi & d->enable_hi; |
| 117 |
break; |
| 118 |
|
| 119 |
case 0x14: |
| 120 |
if (writeflag == MEM_READ) |
| 121 |
odata = d->enable_hi; |
| 122 |
else { |
| 123 |
int old_assert = (d->status_lo & d->enable_lo |
| 124 |
|| d->status_hi & d->enable_hi); |
| 125 |
int new_assert; |
| 126 |
d->enable_hi = idata; |
| 127 |
|
| 128 |
new_assert = (d->status_lo & d->enable_lo || |
| 129 |
d->status_hi & d->enable_hi); |
| 130 |
|
| 131 |
if (old_assert && !new_assert) |
| 132 |
INTERRUPT_DEASSERT(d->cpu_irq); |
| 133 |
else if (!old_assert && new_assert) |
| 134 |
INTERRUPT_ASSERT(d->cpu_irq); |
| 135 |
} |
| 136 |
break; |
| 137 |
|
| 138 |
case 0x18: |
| 139 |
if (writeflag == MEM_WRITE) { |
| 140 |
int old_assert = (d->status_lo & d->enable_lo |
| 141 |
|| d->status_hi & d->enable_hi); |
| 142 |
int new_assert; |
| 143 |
d->status_hi &= ~idata; |
| 144 |
|
| 145 |
new_assert = (d->status_lo & d->enable_lo || |
| 146 |
d->status_hi & d->enable_hi); |
| 147 |
|
| 148 |
if (old_assert && !new_assert) |
| 149 |
INTERRUPT_DEASSERT(d->cpu_irq); |
| 150 |
else if (!old_assert && new_assert) |
| 151 |
INTERRUPT_ASSERT(d->cpu_irq); |
| 152 |
} |
| 153 |
break; |
| 154 |
|
| 155 |
case 0x20: |
| 156 |
if (writeflag == MEM_READ) |
| 157 |
odata = d->status_lo & d->enable_lo; |
| 158 |
break; |
| 159 |
|
| 160 |
case 0x24: |
| 161 |
if (writeflag == MEM_READ) |
| 162 |
odata = d->enable_lo; |
| 163 |
else { |
| 164 |
int old_assert = (d->status_lo & d->enable_lo |
| 165 |
|| d->status_hi & d->enable_hi); |
| 166 |
int new_assert; |
| 167 |
d->enable_lo = idata; |
| 168 |
|
| 169 |
new_assert = (d->status_lo & d->enable_lo || |
| 170 |
d->status_hi & d->enable_hi); |
| 171 |
|
| 172 |
if (old_assert && !new_assert) |
| 173 |
INTERRUPT_DEASSERT(d->cpu_irq); |
| 174 |
else if (!old_assert && new_assert) |
| 175 |
INTERRUPT_ASSERT(d->cpu_irq); |
| 176 |
} |
| 177 |
break; |
| 178 |
|
| 179 |
case 0x28: |
| 180 |
if (writeflag == MEM_WRITE) { |
| 181 |
int old_assert = (d->status_lo & d->enable_lo |
| 182 |
|| d->status_hi & d->enable_hi); |
| 183 |
int new_assert; |
| 184 |
d->status_lo &= ~idata; |
| 185 |
|
| 186 |
new_assert = (d->status_lo & d->enable_lo || |
| 187 |
d->status_hi & d->enable_hi); |
| 188 |
|
| 189 |
if (old_assert && !new_assert) |
| 190 |
INTERRUPT_DEASSERT(d->cpu_irq); |
| 191 |
else if (!old_assert && new_assert) |
| 192 |
INTERRUPT_ASSERT(d->cpu_irq); |
| 193 |
} |
| 194 |
break; |
| 195 |
|
| 196 |
case 0x1c: |
| 197 |
case 0x2c: |
| 198 |
/* Avoid a debug message. */ |
| 199 |
break; |
| 200 |
#endif |
| 201 |
default:if (writeflag == MEM_WRITE) { |
| 202 |
fatal("[ openpic: unimplemented write to " |
| 203 |
"offset 0x%x: data=0x%x ]\n", (int) |
| 204 |
relative_addr, (int)idata); |
| 205 |
} else { |
| 206 |
fatal("[ openpic: unimplemented read from " |
| 207 |
"offset 0x%x ]\n", (int)relative_addr); |
| 208 |
} |
| 209 |
} |
| 210 |
|
| 211 |
if (writeflag == MEM_READ) |
| 212 |
memory_writemax64(cpu, data, len, odata); |
| 213 |
|
| 214 |
return 1; |
| 215 |
} |
| 216 |
|
| 217 |
|
| 218 |
DEVINIT(openpic) |
| 219 |
{ |
| 220 |
struct openpic_data *d; |
| 221 |
int i; |
| 222 |
|
| 223 |
CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data))); |
| 224 |
memset(d, 0, sizeof(struct openpic_data)); |
| 225 |
|
| 226 |
/* Connect to the CPU interrupt pin: */ |
| 227 |
INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq); |
| 228 |
|
| 229 |
/* |
| 230 |
* Register the 126 OpenPIC interrupts |
| 231 |
*/ |
| 232 |
for (i=0; i<126; i++) { |
| 233 |
struct interrupt template; |
| 234 |
char n[300]; |
| 235 |
snprintf(n, sizeof(n), "%s.openpic.%i", |
| 236 |
devinit->interrupt_path, i); |
| 237 |
memset(&template, 0, sizeof(template)); |
| 238 |
template.line = 1 << i; |
| 239 |
template.name = n; |
| 240 |
template.extra = d; |
| 241 |
template.interrupt_assert = openpic_lo_interrupt_assert; |
| 242 |
template.interrupt_deassert = openpic_lo_interrupt_deassert; |
| 243 |
interrupt_handler_register(&template); |
| 244 |
} |
| 245 |
|
| 246 |
memory_device_register(devinit->machine->memory, "openpic", |
| 247 |
devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL); |
| 248 |
|
| 249 |
return 1; |
| 250 |
} |
| 251 |
|
Parent Directory
| 
Revision Log