/[gxemul]/trunk/src/devices/dev_openpic.c
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Contents of /trunk/src/devices/dev_openpic.c

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Revision 44 - (show annotations)
Mon Oct 8 16:22:56 2007 UTC (16 years, 5 months ago) by dpavlin
Original Path: trunk/src/devices/dev_gc.c
File MIME type: text/plain
File size: 7073 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1632 2007/09/11 21:46:35 debug Exp $
20070616	Implementing the MIPS32/64 revision 2 "ror" instruction.
20070617	Adding a struct for each physpage which keeps track of which
		ranges within that page (base offset, length) that are
		continuously translatable. When running with native code
		generation enabled (-b), a range is added after each read-
		ahead loop.
		Experimenting with using the physical program counter sample
		data (implemented 20070608) together with the "translatable
		range" information, to figure out which physical address ranges
		would be worth translating to native code (if the number of
		samples falling within a range is above a certain threshold).
20070618	Adding automagic building of .index comment files for
		src/file/, src/promemul/, src src/useremul/ as well.
		Adding a "has been translated" bit to the ranges, so that only
		not-yet-translated ranges will be sampled.
20070619	Moving src/cpu.c and src/memory_rw.c into src/cpus/,
		src/device.c into src/devices/, and src/machine.c into
		src/machines/.
		Creating a skeleton cc/ld native backend module; beginning on
		the function which will detect cc command line, etc.
20070620	Continuing on the native code generation infrastructure.
20070621	Moving src/x11.c and src/console.c into a new src/console/
		subdir (for everything that is console or framebuffer related).
		Moving src/symbol*.c into a new src/symbol/, which should
		contain anything that is symbol handling related.
20070624	Making the program counter sampling threshold a "settings
		variable" (sampling_threshold), i.e. it can now be changed
		during runtime.
		Switching the RELEASE notes format from plain text to HTML.
		If the TMPDIR environment variable is set, it is used instead
		of "/tmp" for temporary files.
		Continuing on the cc/ld backend: simple .c code is generated,
		the compiler and linker are called, etc.
		Adding detection of host architecture to the configure script
		(again), and adding icache invalidation support (only
		implemented for Alpha hosts so far).
20070625	Simplifying the program counter sampling mechanism.
20070626	Removing the cc/ld native code generation stuff, program
		counter sampling, etc; it would not have worked well in the
		general case.
20070627	Removing everything related to native code generation.
20070629	Removing the (practically unusable) support for multiple
		emulations. (The single emulation allowed now still supports
		multiple simultaneous machines, as before.)
		Beginning on PCCTWO and M88K interrupts.
20070723	Adding a dummy skeleton for emulation of M32R processors.
20070901	Fixing a warning found by "gcc version 4.3.0 20070817
		(experimental)" on amd64.
20070905	Removing some more traces of the old "multiple emulations"
		code.
		Also looking in /usr/local/include and /usr/local/lib for
		X11 libs, when running configure.
20070909	Minor updates to the guest OS install instructions, in
		preparation for the NetBSD 4.0 release.
20070918	More testing of NetBSD 4.0 RC1.

1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id: dev_gc.c,v 1.14 2007/09/11 21:42:52 debug Exp $
28 *
29 * COMMENT: Grand Central Interrupt controller (used by MacPPC)
30 */
31
32 #include <stdio.h>
33 #include <stdlib.h>
34 #include <string.h>
35
36 #include "cpu.h"
37 #include "device.h"
38 #include "machine.h"
39 #include "memory.h"
40 #include "misc.h"
41
42
43 #define DEV_GC_LENGTH 0x100
44
45 struct gc_data {
46 struct interrupt cpu_irq;
47
48 uint32_t status_hi;
49 uint32_t status_lo;
50 uint32_t enable_hi;
51 uint32_t enable_lo;
52 };
53
54
55 void gc_hi_interrupt_assert(struct interrupt *interrupt)
56 {
57 struct gc_data *d = interrupt->extra;
58 d->status_hi |= interrupt->line;
59 if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
60 INTERRUPT_ASSERT(d->cpu_irq);
61 }
62 void gc_hi_interrupt_deassert(struct interrupt *interrupt)
63 {
64 struct gc_data *d = interrupt->extra;
65 d->status_hi &= ~interrupt->line;
66 if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
67 INTERRUPT_DEASSERT(d->cpu_irq);
68 }
69 void gc_lo_interrupt_assert(struct interrupt *interrupt)
70 {
71 struct gc_data *d = interrupt->extra;
72 d->status_lo |= interrupt->line;
73 if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
74 INTERRUPT_ASSERT(d->cpu_irq);
75 }
76 void gc_lo_interrupt_deassert(struct interrupt *interrupt)
77 {
78 struct gc_data *d = interrupt->extra;
79 d->status_lo &= ~interrupt->line;
80 if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
81 INTERRUPT_DEASSERT(d->cpu_irq);
82 }
83
84
85 DEVICE_ACCESS(gc)
86 {
87 struct gc_data *d = extra;
88 uint64_t idata = 0, odata = 0;
89
90 if (writeflag == MEM_WRITE)
91 idata = memory_readmax64(cpu, data, len);
92
93 switch (relative_addr) {
94
95 #if 0
96 #define INT_STATE_REG_H (interrupt_reg + 0x00)
97 #define INT_ENABLE_REG_H (interrupt_reg + 0x04)
98 #define INT_CLEAR_REG_H (interrupt_reg + 0x08)
99 #define INT_LEVEL_REG_H (interrupt_reg + 0x0c)
100 #define INT_STATE_REG_L (interrupt_reg + 0x10)
101 #define INT_ENABLE_REG_L (interrupt_reg + 0x14)
102 #define INT_CLEAR_REG_L (interrupt_reg + 0x18)
103 #define INT_LEVEL_REG_L (interrupt_reg + 0x1c)
104 #endif
105
106 case 0x10:
107 if (writeflag == MEM_READ)
108 odata = d->status_hi & d->enable_hi;
109 break;
110
111 case 0x14:
112 if (writeflag == MEM_READ)
113 odata = d->enable_hi;
114 else {
115 int old_assert = (d->status_lo & d->enable_lo
116 || d->status_hi & d->enable_hi);
117 int new_assert;
118 d->enable_hi = idata;
119
120 new_assert = (d->status_lo & d->enable_lo ||
121 d->status_hi & d->enable_hi);
122
123 if (old_assert && !new_assert)
124 INTERRUPT_DEASSERT(d->cpu_irq);
125 else if (!old_assert && new_assert)
126 INTERRUPT_ASSERT(d->cpu_irq);
127 }
128 break;
129
130 case 0x18:
131 if (writeflag == MEM_WRITE) {
132 int old_assert = (d->status_lo & d->enable_lo
133 || d->status_hi & d->enable_hi);
134 int new_assert;
135 d->status_hi &= ~idata;
136
137 new_assert = (d->status_lo & d->enable_lo ||
138 d->status_hi & d->enable_hi);
139
140 if (old_assert && !new_assert)
141 INTERRUPT_DEASSERT(d->cpu_irq);
142 else if (!old_assert && new_assert)
143 INTERRUPT_ASSERT(d->cpu_irq);
144 }
145 break;
146
147 case 0x20:
148 if (writeflag == MEM_READ)
149 odata = d->status_lo & d->enable_lo;
150 break;
151
152 case 0x24:
153 if (writeflag == MEM_READ)
154 odata = d->enable_lo;
155 else {
156 int old_assert = (d->status_lo & d->enable_lo
157 || d->status_hi & d->enable_hi);
158 int new_assert;
159 d->enable_lo = idata;
160
161 new_assert = (d->status_lo & d->enable_lo ||
162 d->status_hi & d->enable_hi);
163
164 if (old_assert && !new_assert)
165 INTERRUPT_DEASSERT(d->cpu_irq);
166 else if (!old_assert && new_assert)
167 INTERRUPT_ASSERT(d->cpu_irq);
168 }
169 break;
170
171 case 0x28:
172 if (writeflag == MEM_WRITE) {
173 int old_assert = (d->status_lo & d->enable_lo
174 || d->status_hi & d->enable_hi);
175 int new_assert;
176 d->status_lo &= ~idata;
177
178 new_assert = (d->status_lo & d->enable_lo ||
179 d->status_hi & d->enable_hi);
180
181 if (old_assert && !new_assert)
182 INTERRUPT_DEASSERT(d->cpu_irq);
183 else if (!old_assert && new_assert)
184 INTERRUPT_ASSERT(d->cpu_irq);
185 }
186 break;
187
188 case 0x1c:
189 case 0x2c:
190 /* Avoid a debug message. */
191 break;
192
193 default:if (writeflag == MEM_WRITE) {
194 fatal("[ gc: unimplemented write to "
195 "offset 0x%x: data=0x%x ]\n", (int)
196 relative_addr, (int)idata);
197 } else {
198 fatal("[ gc: unimplemented read from "
199 "offset 0x%x ]\n", (int)relative_addr);
200 }
201 }
202
203 if (writeflag == MEM_READ)
204 memory_writemax64(cpu, data, len, odata);
205
206 return 1;
207 }
208
209
210 DEVINIT(gc)
211 {
212 struct gc_data *d;
213 int i;
214
215 CHECK_ALLOCATION(d = malloc(sizeof(struct gc_data)));
216 memset(d, 0, sizeof(struct gc_data));
217
218 /* Connect to the CPU interrupt pin: */
219 INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
220
221 /*
222 * Register the 64 Grand Central interrupts (32 lo, 32 hi):
223 */
224 for (i=0; i<32; i++) {
225 struct interrupt template;
226 char n[300];
227 snprintf(n, sizeof(n), "%s.gc.lo.%i",
228 devinit->interrupt_path, i);
229 memset(&template, 0, sizeof(template));
230 template.line = 1 << i;
231 template.name = n;
232 template.extra = d;
233 template.interrupt_assert = gc_lo_interrupt_assert;
234 template.interrupt_deassert = gc_lo_interrupt_deassert;
235 interrupt_handler_register(&template);
236
237 snprintf(n, sizeof(n), "%s.gc.hi.%i",
238 devinit->interrupt_path, i);
239 memset(&template, 0, sizeof(template));
240 template.line = 1 << i;
241 template.name = n;
242 template.extra = d;
243 template.interrupt_assert = gc_hi_interrupt_assert;
244 template.interrupt_deassert = gc_hi_interrupt_deassert;
245 interrupt_handler_register(&template);
246 }
247
248 memory_device_register(devinit->machine->memory, "gc",
249 devinit->addr, DEV_GC_LENGTH, dev_gc_access, d, DM_DEFAULT, NULL);
250
251 return 1;
252 }
253

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