--- trunk/src/devices/dev_openpic.c	2007/10/14 13:46:39	67
+++ trunk/src/devices/dev_openpic.c	2007/10/14 16:53:47	71
@@ -82,6 +82,10 @@
 		INTERRUPT_DEASSERT(d->cpu_irq);
 }
 
+/*
+ * FIXME acitvity is never sat
+ */
+
 #define OPENPIC_MASK                            0x80000000
 #define OPENPIC_ACTIVITY                        0x40000000      /* Read Only */
 #define OPENPIC_PRIORITY_MASK                   0x000f0000
@@ -100,33 +104,35 @@
 DEVICE_ACCESS(openpic)
 {
 //	struct openpic_data *d = extra;
-	uint64_t idata = 0, odata = 0, decoded = 0;
+	uint64_t idata = 0, odata = 0;
 
 	if (writeflag == MEM_WRITE) {
 		idata = memory_readmax64(cpu, data, len);
-		decoded =
+		// shuffle byte order
+		idata =
 			( idata & 0x000000ff ) << 24 |
 			( idata & 0x0000ff00 ) << 8  |
 			( idata & 0x00ff0000 ) >> 8  |
 			( idata & 0xff000000 ) >> 24 ;
 
 		uint64_t priority,vector, active;
-		priority = ( decoded & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT;
-		vector   = ( decoded & OPENPIC_VECTOR_MASK );
-		active	 = ( decoded & OPENPIC_ACTIVITY );
+		priority = ( idata & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT;
+		vector   = ( idata & OPENPIC_VECTOR_MASK );
+		active	 = ( idata & OPENPIC_ACTIVITY );
 
-		debug("[ openpic: WRITE %05x | %08x => %08x | priority: %x vector: 0x%02x %d active: %x ]\n",
-			(int)relative_addr, (int)idata, (int)decoded, (int)priority, (int)vector, (int)vector, (int)active );
+		debug("[ openpic: WRITE %05x | %08x | priority: %x vector: 0x%02x %d active: %x ]\n",
+			(int)relative_addr, (int)idata, (int)priority, (int)vector, (int)vector, (int)active );
 	}
 
 	switch (relative_addr) {
 
+	// version
 	case 0x00:
 		if (writeflag == MEM_READ) {
-			// version 1.2
-			odata = 0x02000000;
-			fatal("[ openpic: read from "
-			    "offset 0x%x (OpenPIC version) = %x]\n", (int)
+			// version 1.x, so 2 -> 1.2
+			odata = 2;
+			fatal("[ openpic: read version "
+			    "offset 0x%x = 1.%d]\n", (int)
 			    relative_addr, (int)odata);
 		}
 		fatal("[ openpic: unimplemented write to "
@@ -134,6 +140,19 @@
 		    relative_addr, (int)idata);
 		break;
 
+	// global timer frequency
+	case 0xf0:
+		if (writeflag == MEM_READ) {
+			odata = 170 * 1000000;	// MHz
+			fatal("[ openpic: read global timer frequency "
+			    "offset 0x%x = %x]\n", (int)
+			    relative_addr, (int)odata);
+		}
+		fatal("[ openpic: unimplemented write to "
+		    "offset 0x%x: data=0x%x ]\n", (int)
+		    relative_addr, (int)idata);
+		break;
+
 #if 0
 #define INT_STATE_REG_H  (interrupt_reg + 0x00)
 #define INT_ENABLE_REG_H (interrupt_reg + 0x04)
@@ -231,18 +250,32 @@
 		/*  Avoid a debug message.  */
 		break;
 #endif
-	default:if (writeflag == MEM_WRITE) {
+	default:
+		if (writeflag == MEM_WRITE) {
 			fatal("[ openpic: unimplemented write to "
-			    "offset 0x%x: data=0x%x ]\n", (int)
-			    relative_addr, (int)idata);
+				"offset 0x%x idata = %x ]\n",
+				(int)relative_addr, (int)idata
+			);
 		} else {
 			fatal("[ openpic: unimplemented read from "
-			    "offset 0x%x ]\n", (int)relative_addr);
+				"offset 0x%x odata = %x ]\n",
+				(int)relative_addr, (int)odata
+			);
 		}
 	}
 
-	if (writeflag == MEM_READ)
+	if (writeflag == MEM_READ) {
+		// shuffle byte order
+		odata =
+			( odata & 0x000000ff ) << 24 |
+			( odata & 0x0000ff00 ) << 8  |
+			( odata & 0x00ff0000 ) >> 8  |
+			( odata & 0xff000000 ) >> 24 ;
 		memory_writemax64(cpu, data, len, odata);
+		debug("[ openpic: READ %05x | %08x ]\n",
+			(int)relative_addr, (int)odata
+		);
+	}
 
 	return 1;
 }
@@ -274,6 +307,7 @@
 		template.interrupt_assert = openpic_lo_interrupt_assert;
 		template.interrupt_deassert = openpic_lo_interrupt_deassert;
 		interrupt_handler_register(&template);
+//		debug("[ openpic: added interrupt %s ]\n", n);
 	}
 
 	memory_device_register(devinit->machine->memory, "openpic",