82 |
INTERRUPT_DEASSERT(d->cpu_irq); |
INTERRUPT_DEASSERT(d->cpu_irq); |
83 |
} |
} |
84 |
|
|
85 |
|
#define OPENPIC_MASK 0x80000000 |
86 |
|
#define OPENPIC_ACTIVITY 0x40000000 /* Read Only */ |
87 |
|
#define OPENPIC_PRIORITY_MASK 0x000f0000 |
88 |
|
#define OPENPIC_PRIORITY_SHIFT 16 |
89 |
|
#define OPENPIC_VECTOR_MASK 0x000000ff |
90 |
|
|
91 |
|
#define OPENPIC_VEC_TIMER 64 /* and up */ |
92 |
|
#define OPENPIC_VEC_IPI 72 /* and up */ |
93 |
|
#define OPENPIC_VEC_SPURIOUS 127 |
94 |
|
|
95 |
DEVICE_ACCESS(openpic) |
DEVICE_ACCESS(openpic) |
96 |
{ |
{ |
100 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
101 |
idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
102 |
|
|
103 |
|
uint64_t priority,vector, active; |
104 |
|
priority = ( relative_addr & 0xf000 ); |
105 |
|
vector = ( relative_addr & 0x00ff ); |
106 |
|
active = ( relative_addr & 0x4000 ); |
107 |
|
|
108 |
|
debug("[ openpic: access at %04x -> priority: %x vector: 0x%02x %d active: %x ]\n", |
109 |
|
(int)relative_addr, (int)priority, (int)vector, (int)vector, (int)active ); |
110 |
|
|
111 |
switch (relative_addr) { |
switch (relative_addr) { |
112 |
|
|
113 |
|
case 0x00: |
114 |
|
if (writeflag == MEM_READ) { |
115 |
|
// version 1.2 |
116 |
|
odata = 0x02000000; |
117 |
|
fatal("[ openpic: read from " |
118 |
|
"offset 0x%x (OpenPIC version) = %x]\n", (int) |
119 |
|
relative_addr, (int)odata); |
120 |
|
} |
121 |
|
fatal("[ openpic: unimplemented write to " |
122 |
|
"offset 0x%x: data=0x%x (OpenPIC version) ]\n", (int) |
123 |
|
relative_addr, (int)idata); |
124 |
|
break; |
125 |
|
|
126 |
#if 0 |
#if 0 |
127 |
#define INT_STATE_REG_H (interrupt_reg + 0x00) |
#define INT_STATE_REG_H (interrupt_reg + 0x00) |
128 |
#define INT_ENABLE_REG_H (interrupt_reg + 0x04) |
#define INT_ENABLE_REG_H (interrupt_reg + 0x04) |